Apple-1-HW/verilog-apple-one
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added pretend UART RX waveform

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Alan Garfield 2018-01-28 00:21:48 +11:00
parent b42567e759
commit f081eb674f
1 changed files with 22 additions and 7 deletions
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29
iverilog/apple1_tb.v
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@ -19,7 +19,7 @@
// //
// Author.....: Niels A. Moseley // Author.....: Niels A. Moseley
// Date.......: 26-1-2018 // Date.......: 26-1-2018
// //
`timescale 1ns/1ps `timescale 1ns/1ps
@ -28,7 +28,7 @@ module apple1_tb;
reg clk25, uart_rx, rst_n; reg clk25, uart_rx, rst_n;
wire uart_tx, uart_cts; wire uart_tx, uart_cts;
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Setup dumping of data for inspection // Setup dumping of data for inspection
initial begin initial begin
@ -106,8 +106,8 @@ module apple1_tb;
force core_top.my_cpu.arlet_cpu.ALU.temp_h = 0; force core_top.my_cpu.arlet_cpu.ALU.temp_h = 0;
clk25 = 1'b0; clk25 = 1'b0;
uart_rx = 1'b0; uart_rx = 1'b1;
rst_n = 1'b0; rst_n = 1'b0;
#40 rst_n = 1'b1; #40 rst_n = 1'b1;
release core_top.clk_div; release core_top.clk_div;
@ -185,18 +185,33 @@ module apple1_tb;
$display("Starting..."); $display("Starting...");
$dumpfile("apple1_top_tb.vcd"); $dumpfile("apple1_top_tb.vcd");
$dumpvars; $dumpvars;
#180000
uart_rx = 1'b0;
#400
uart_rx = 1'b1;
#400
uart_rx = 1'b0;
#400
uart_rx = 1'b1;
#800
uart_rx = 1'b0;
#1600
uart_rx = 1'b1;
#1000000 $display("Stopping..."); #1000000 $display("Stopping...");
$finish; $finish;
end end
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Clock // Clock
always always
#20 clk25 = !clk25; #20 clk25 = !clk25;
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Core of system // Core of system
apple1 #( apple1 #(
"../roms/ram.hex", "../roms/ram.hex",