11 Commits

Author	SHA1	Message	Date
Alan Garfield	526538a685	fixed param paths for yosys, may need more work	2018-02-14 15:27:36 +11:00
Olof Kindgren	2226afe669	Expose ROM/RAM files as top-level parameters ... This allows file names to be overridden at compile-time. It also gets rid of the ifdef SIM in the verilog components	2018-02-12 14:04:00 +01:00
Alan Garfield	a4f13a87fe	updated ROM paths to handle new board/buildenv structure	2018-02-12 08:26:57 +11:00
Alan Garfield	b2ebc23e3a	added license headers and tidied up	2018-01-29 22:15:21 +11:00
Alan Garfield	119d077e1a	Fixed differences for iceube2 and yosys	2018-01-29 21:36:32 +11:00
Alan Garfield	2717184e71	Added yosys support again, yay for FOSS!	2018-01-29 17:45:01 +11:00
Alan Garfield	69f1b53e18	added basic rom and fix uart issue on HX	2018-01-28 15:02:51 +11:00
Alan Garfield	bcaf9e6962	Yay got iverilog sim working!	2018-01-27 22:13:52 +11:00
Alan Garfield	04323a6256	more moving around, added params for hex files	2018-01-27 14:27:10 +11:00
Niels Moseley	cca11b7925	Added iverilog simulation support	2018-01-26 23:32:31 +01:00
Alan Garfield	7bdccf3d1a	move things around.	2018-01-27 00:21:05 +11:00