Apple-1-HW/verilog-apple-one
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72 Commits 3 Branches 0 Tags 6.9 MiB
20919fa726
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5 Commits

Author SHA1 Message Date
Alan Garfield
20919fa726 wip of the pipeline VGA module. stupid yosys bug, but testbench looks ok 2018-02-05 00:12:06 +11:00
Alan Garfield
2432225d01 Initial VGA working with the apple one output. YAY! 2018-01-31 00:48:47 +11:00
Alan Garfield
400cdd75d0 added missing vga roms 2018-01-29 22:36:28 +11:00
Alan Garfield
04323a6256 more moving around, added params for hex files 2018-01-27 14:27:10 +11:00
Alan Garfield
92dd0d2e71 moved sources into rtl to clean up root 2018-01-12 13:40:44 +11:00