Apple-1-HW/verilog-apple-one
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Code Issues Projects Releases Wiki Activity
71 Commits 3 Branches 0 Tags 6.9 MiB
2432225d01
Commit Graph

36 Commits

Author SHA1 Message Date
Alan Garfield
2432225d01 Initial VGA working with the apple one output. YAY! 2018-01-31 00:48:47 +11:00
Alan Garfield
451bff1592 fiddled the vga module a little 2018-01-30 00:19:21 +11:00
Alan Garfield
4fef9bc10b Initial VGA module, still WIP, just outputs fixed VRAM 2018-01-29 22:53:16 +11:00
Alan Garfield
b2ebc23e3a added license headers and tidied up 2018-01-29 22:15:21 +11:00
Alan Garfield
119d077e1a Fixed differences for iceube2 and yosys 2018-01-29 21:36:32 +11:00
Alan Garfield
474cabbab0 Made core neater and trying to get naming better 2018-01-29 21:00:38 +11:00
Alan Garfield
2717184e71 Added yosys support again, yay for FOSS! 2018-01-29 17:45:01 +11:00
Niels Moseley
586b006e88 PS/2 keyboard seems to be working including the shift key. It needs debouncing, however 2018-01-29 00:39:24 +01:00
Niels Moseley
5c87a46445 Added ps/2 shift key support 2018-01-28 23:56:02 +01:00
Niels Moseley
25f08eeb1d PS/2 keyboard now has ASCII translation, but shift isn't working yet 2018-01-28 23:41:27 +01:00
Niels Moseley
fe05766894 Fixed address lines of Basic ROM 2018-01-28 20:18:56 +01:00
Alan Garfield
69f1b53e18 added basic rom and fix uart issue on HX 2018-01-28 15:02:51 +11:00
Niels Moseley
d280d2abaa Added basic ps2 keyboard interface block 2018-01-28 02:00:21 +01:00
Niels Moseley
15f476b9eb Fixed irq_n and nmi_n active low/high bug 2018-01-27 22:58:07 +01:00
Niels Moseley
645ec26081 Added missing 7-segment display driver for DE0 board 2018-01-27 18:47:56 +01:00
Niels Moseley
c244a3bc5d Fixed bug in pc_monitor signal 2018-01-27 18:15:19 +01:00
Niels Moseley
6823d0e3f9 Added 6502 PC monitoring 2018-01-27 18:11:33 +01:00
Niels Moseley
0527dbb999 Updated DE0 top level and Quartus DE0 project to new directory layout 2018-01-27 16:01:27 +01:00
Niels Moseley
a60620e6ec Merge remote-tracking branch 'upstream/master' into boards 2018-01-27 14:45:21 +01:00
Niels Moseley
b61b490e4b added missing DE0 top level 2018-01-27 14:42:15 +01:00
Alan Garfield
0fc84e0b37 added reset logic to uart and CPU 2018-01-28 00:23:09 +11:00
Alan Garfield
abba4eeee6 added reset to cpu registers and made uart ignore first tx 2018-01-27 22:56:28 +11:00
Alan Garfield
bcaf9e6962 Yay got iverilog sim working! 2018-01-27 22:13:52 +11:00
Alan Garfield
c4d42fae3c fixed testbench and split CPU cores 2018-01-27 17:00:33 +11:00
Alan Garfield
04323a6256 more moving around, added params for hex files 2018-01-27 14:27:10 +11:00
Alan Garfield
149334259d Cleaned up mess, and added HX8K board top file 2018-01-27 13:40:59 +11:00
Niels Moseley
5e3f065223 Forced some internal CPU signals at start of simuation to get rid of undefined signals. Also made sure hard_reset signal is never undefined 2018-01-27 01:21:47 +01:00
Niels Moseley
f19344cf58 Editted CPU and testbench for better simulation 2018-01-27 00:48:05 +01:00
Niels Moseley
9465e0c14d Added synchronous reset to clk enable divider to avoid undefined logic state in simulation 2018-01-26 23:41:58 +01:00
Niels Moseley
cca11b7925 Added iverilog simulation support 2018-01-26 23:32:31 +01:00
Niels Moseley
34078e13ae Fixed cpu_clken wire -> reg 2018-01-26 22:59:43 +01:00
Niels Moseley
f067774293 Added timing constraints and pin assignments to DE0 board. Integrated the 1MHz clock enable signal into the core top level. Top level now requires a 25MHz clock signal. 2018-01-26 22:38:46 +01:00
Niels Moseley
9beb3e5f5e Disabled ice40 specific define and clock generation. Added Terasic DE0 Quartus files. 2018-01-26 21:29:12 +01:00
Alan Garfield
7bdccf3d1a move things around. 2018-01-27 00:21:05 +11:00
Alan Garfield
2b91bb3841 moved some files around to clean things up a bit 2018-01-12 15:17:35 +11:00
Alan Garfield
92dd0d2e71 moved sources into rtl to clean up root 2018-01-12 13:40:44 +11:00