Apple-1-HW/verilog-apple-one
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68 Commits 3 Branches 0 Tags 6.9 MiB
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3 Commits

Author SHA1 Message Date
Niels Moseley
ac2d460f92 Added SIM define to run_testbench.bat 2018-01-27 22:32:51 +01:00
Alan Garfield
c4d42fae3c fixed testbench and split CPU cores 2018-01-27 17:00:33 +11:00
Niels Moseley
cca11b7925 Added iverilog simulation support 2018-01-26 23:32:31 +01:00