Apple-1-HW/verilog-apple-one
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65 Commits 3 Branches 0 Tags 6.9 MiB
Commit Graph

10 Commits

Author SHA1 Message Date
Alan Garfield
474cabbab0 Made core neater and trying to get naming better 2018-01-29 21:00:38 +11:00
Niels Moseley
15f476b9eb Fixed irq_n and nmi_n active low/high bug 2018-01-27 22:58:07 +01:00
Niels Moseley
c244a3bc5d Fixed bug in pc_monitor signal 2018-01-27 18:15:19 +01:00
Niels Moseley
6823d0e3f9 Added 6502 PC monitoring 2018-01-27 18:11:33 +01:00
Alan Garfield
0fc84e0b37 added reset logic to uart and CPU 2018-01-28 00:23:09 +11:00
Alan Garfield
abba4eeee6 added reset to cpu registers and made uart ignore first tx 2018-01-27 22:56:28 +11:00
Alan Garfield
bcaf9e6962 Yay got iverilog sim working! 2018-01-27 22:13:52 +11:00
Alan Garfield
c4d42fae3c fixed testbench and split CPU cores 2018-01-27 17:00:33 +11:00
Niels Moseley
f19344cf58 Editted CPU and testbench for better simulation 2018-01-27 00:48:05 +01:00
Alan Garfield
7bdccf3d1a move things around. 2018-01-27 00:21:05 +11:00