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Author	SHA1	Message	Date
Alan Garfield	bcaf9e6962	Yay got iverilog sim working!	2018-01-27 22:13:52 +11:00
Alan Garfield	c4d42fae3c	fixed testbench and split CPU cores	2018-01-27 17:00:33 +11:00
Alan Garfield	04323a6256	more moving around, added params for hex files	2018-01-27 14:27:10 +11:00
Alan Garfield	0ca73c561a	fixed project path for HX8K	2018-01-27 13:58:03 +11:00
Alan Garfield	401e987548	Merge pull request #5 from alangarf/boards ... Implement support for boards	2018-01-27 13:52:04 +11:00
Alan Garfield	149334259d	Cleaned up mess, and added HX8K board top file	2018-01-27 13:40:59 +11:00
Alan Garfield	305d9b614b	Merge pull request #3 from trcwm/boards ... Disabled ice40 specific define and clock generation. Added Terasic DE…	2018-01-27 12:54:38 +11:00
Niels Moseley	5e3f065223	Forced some internal CPU signals at start of simuation to get rid of undefined signals. Also made sure hard_reset signal is never undefined	2018-01-27 01:21:47 +01:00
Niels Moseley	f19344cf58	Editted CPU and testbench for better simulation	2018-01-27 00:48:05 +01:00
Niels Moseley	9465e0c14d	Added synchronous reset to clk enable divider to avoid undefined logic state in simulation	2018-01-26 23:41:58 +01:00
Niels Moseley	cca11b7925	Added iverilog simulation support	2018-01-26 23:32:31 +01:00
Niels Moseley	34078e13ae	Fixed cpu_clken wire -> reg	2018-01-26 22:59:43 +01:00
Niels Moseley	f067774293	Added timing constraints and pin assignments to DE0 board. Integrated the 1MHz clock enable signal into the core top level. Top level now requires a 25MHz clock signal.	2018-01-26 22:38:46 +01:00
Niels Moseley	9beb3e5f5e	Disabled ice40 specific define and clock generation. Added Terasic DE0 Quartus files.	2018-01-26 21:29:12 +01:00
Alan Garfield	7bdccf3d1a	move things around.	2018-01-27 00:21:05 +11:00
Alan Garfield	2b91bb3841	moved some files around to clean things up a bit	2018-01-12 15:17:35 +11:00
Alan Garfield	50d80bedcd	Merge pull request #1 from alangarf/alangarf-readme ... Updated readme	2018-01-12 14:42:57 +11:00
Alan Garfield	83786cc594	Update README.md	2018-01-12 14:42:42 +11:00
Alan Garfield	ed76bfaa0a	Added HX8K board image	2018-01-12 14:39:58 +11:00
Alan Garfield	51fc482c08	Update README.md	2018-01-12 14:36:55 +11:00
Alan Garfield	c6a1c6b869	Update README.md	2018-01-12 14:34:36 +11:00
Alan Garfield	b70f32937c	Update README.md	2018-01-12 14:32:42 +11:00
Alan Garfield	080e3e5cef	Update README with new logo	2018-01-12 14:17:39 +11:00
Alan Garfield	92dd0d2e71	moved sources into rtl to clean up root	2018-01-12 13:40:44 +11:00
Alan Garfield	697bd34798	Fixed issue with basic ROM	2018-01-12 01:01:34 +11:00
Alan Garfield	158510c299	Added basic ROM and fiddled things ... Clock now runs at 6MHz while I try to simplify things to figure out a CPU bug	2018-01-10 16:39:18 +11:00
Alan Garfield	ae1d371e37	Added small images	2018-01-02 01:33:47 +11:00
Alan Garfield	3f9d786769	Added basic images of breakout board	2018-01-02 01:28:31 +11:00
Alan Garfield	6b48bdbb05	Update README.md	2018-01-02 01:18:19 +11:00
Alan Garfield	3a69b0eda0	Update README.md	2018-01-02 01:15:44 +11:00
Alan Garfield	5ff6a2ecf3	Update README.md	2018-01-02 01:05:27 +11:00
Alan Garfield	117d18ea54	Update README.md	2018-01-02 01:05:01 +11:00
Alan Garfield	b841685a9a	Update README.md	2018-01-02 01:04:35 +11:00
Alan Garfield	197d6a145e	Update README.md	2018-01-02 00:57:46 +11:00
Alan Garfield	31f20d49b4	Update README.md	2018-01-02 00:56:57 +11:00
Alan Garfield	8aad887a5e	Initial commit	2018-01-02 00:33:20 +11:00
Alan Garfield	e2b390bbd6	Initial commit	2018-01-02 00:23:13 +11:00