7 Commits

Author	SHA1	Message	Date
Niels Moseley	f19344cf58	Editted CPU and testbench for better simulation	2018-01-27 00:48:05 +01:00
Niels Moseley	9465e0c14d	Added synchronous reset to clk enable divider to avoid undefined logic state in simulation	2018-01-26 23:41:58 +01:00
Niels Moseley	34078e13ae	Fixed cpu_clken wire -> reg	2018-01-26 22:59:43 +01:00
Niels Moseley	f067774293	Added timing constraints and pin assignments to DE0 board. Integrated the 1MHz clock enable signal into the core top level. Top level now requires a 25MHz clock signal.	2018-01-26 22:38:46 +01:00
Niels Moseley	9beb3e5f5e	Disabled ice40 specific define and clock generation. Added Terasic DE0 Quartus files.	2018-01-26 21:29:12 +01:00
Alan Garfield	7bdccf3d1a	move things around.	2018-01-27 00:21:05 +11:00
Alan Garfield	2b91bb3841	moved some files around to clean things up a bit	2018-01-12 15:17:35 +11:00