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Apple-1-HW/verilog-apple-one
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04323a625695dbba044e2760353eb1c0a559d03d
verilog-apple-one/boards
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Alan Garfield 04323a6256 more moving around, added params for hex files
2018-01-27 14:27:10 +11:00
..
ice40hx8k
more moving around, added params for hex files
2018-01-27 14:27:10 +11:00
terasic_de0
Added timing constraints and pin assignments to DE0 board. Integrated the 1MHz clock enable signal into the core top level. Top level now requires a 25MHz clock signal.
2018-01-26 22:38:46 +01:00
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