Apple-1-HW/verilog-apple-one
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verilog-apple-one/iverilog
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Niels Moseley 5e3f065223 Forced some internal CPU signals at start of simuation to get rid of undefined signals. Also made sure hard_reset signal is never undefined
2018-01-27 01:21:47 +01:00
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apple1_files.txt Added iverilog simulation support 2018-01-26 23:32:31 +01:00
apple1_top_tb.v Forced some internal CPU signals at start of simuation to get rid of undefined signals. Also made sure hard_reset signal is never undefined 2018-01-27 01:21:47 +01:00
run_testbench.bat Added iverilog simulation support 2018-01-26 23:32:31 +01:00