121 lines
3.8 KiB
Verilog
121 lines
3.8 KiB
Verilog
// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Apple 1 implementation for the Blackeice II ICE40HX8K +
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//
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// Author.....: Lawrence Manning
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// Date.......: 18-04-2024 (inspired by blackice2/apple1_hx8k.v)
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//
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module apple1_top #(
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parameter BASIC_FILENAME = "../../../roms/basic.hex",
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parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
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parameter RAM_FILENAME = "../../../roms/ram.hex",
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parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
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parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
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) (
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input clk, // 50 MHz board clock
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// I/O interface to computer
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input uart_rx, // asynchronous serial data input from computer
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output uart_tx, // asynchronous serial data output to computer
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output uart_cts, // clear to send flag to computer - not used
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// I/O interface to keyboard
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input ps2_clk, // PS/2 keyboard serial clock input
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input ps2_din, // PS/2 keyboard serial data input
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// Outputs to VGA display
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output vga_h_sync, // hozizontal VGA sync pulse
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output vga_v_sync, // vertical VGA sync pulse
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// Outputs to the ADV7123 RGB DAC IC
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output vga_clk,
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output vga_blank_n,
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output [3:0] vga_r, // red VGA signal
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output [3:0] vga_g, // green VGA signal
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output [3:0] vga_b, // blue VGA signal
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// Debugging ports
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output [2:0] led,
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input button, // 1 button on board
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);
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assign vga_clk = clk25;
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assign vga_blank_n = 1;
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// Active low
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assign led[0] = reset_n;
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assign led[1] = 1;
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assign led[2] = 1;
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// ===============================================================
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// System Clock generation (25MHz)
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// ===============================================================
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reg clk25 = 1;
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// generate 25MHz clock from 50MHz master clock
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always @(posedge clk)
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begin
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clk25 <= ~clk25;
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end
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wire vga_bit;
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// set the monochrome base colour here..
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assign vga_r[3:0] = vga_bit ? 4'b1000 : 4'b0000;
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assign vga_g[3:0] = vga_bit ? 4'b1111 : 4'b0000;
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assign vga_b[3:0] = vga_bit ? 4'b1000 : 4'b0000;
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// debounce reset button
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wire reset_n;
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debounce reset_button (
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.clk25(clk25),
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.rst(1'b0),
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.sig_in(button),
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.sig_out(reset_n)
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);
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// apple one main system
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apple1 #(
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.BASIC_FILENAME (BASIC_FILENAME),
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.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
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.RAM_FILENAME (RAM_FILENAME),
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.VRAM_FILENAME (VRAM_FILENAME),
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.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
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) my_apple1(
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.clk25(clk25),
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.rst_n(reset_n),
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.uart_rx(uart_rx),
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.uart_tx(uart_tx),
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.uart_cts(uart_cts),
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.ps2_clk(ps2_clk),
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.ps2_din(ps2_din),
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.ps2_select(1'b1), // PS/2 enabled, UART TX disabled
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// .ps2_select(1'b0), // PS/2 disabled, UART TX enabled
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.vga_h_sync(vga_h_sync),
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.vga_v_sync(vga_v_sync),
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.vga_red(vga_bit),
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.vga_cls(~reset_n),
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);
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endmodule
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