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31 lines
547 B
Verilog
31 lines
547 B
Verilog
module pwr_reset(
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input clk25,
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input rst_n,
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input enable,
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output rst
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);
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reg hard_reset;
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reg [5:0] reset_cnt;
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wire pwr_up_flag = &reset_cnt;
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always @(posedge clk25)
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begin
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if (rst_n == 1'b0)
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begin
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reset_cnt <= 6'b0;
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hard_reset <= 1'b0;
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end
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else if (enable)
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begin
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if (!pwr_up_flag)
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reset_cnt <= reset_cnt + 6'b1;
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hard_reset <= pwr_up_flag;
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end
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end
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assign rst = ~hard_reset;
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endmodule
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