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Apple-1-HW/verilog-apple-one
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149334259d7d1455c6c386b63c994cd17b6954c4
verilog-apple-one/boards
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Alan Garfield 149334259d Cleaned up mess, and added HX8K board top file
2018-01-27 13:40:59 +11:00
..
ice40hx8k
Cleaned up mess, and added HX8K board top file
2018-01-27 13:40:59 +11:00
terasic_de0
Added timing constraints and pin assignments to DE0 board. Integrated the 1MHz clock enable signal into the core top level. Top level now requires a 25MHz clock signal.
2018-01-26 22:38:46 +01:00
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