89 lines
2.7 KiB
Plaintext
89 lines
2.7 KiB
Plaintext
[Project]
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ProjectVersion=2.0
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Version=Lattice Semiconductor Corporation iCEcube - Release: 2017.08.27940 - Build Date: Sep 11 2017 17:40:01
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ProjectName=icecube2
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Vendor=SiliconBlue
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Synthesis=synplify
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ProjectVFiles=../../../../rtl/apple1.v,../../../../rtl/clock.v,../../../../rtl/pwr_reset.v,../../../../rtl/ram.v,../../../../rtl/rom_basic.v,../../../../rtl/rom_wozmon.v,../../../../rtl/boards/tinyfpga_bx/apple1_hx8k.v,../../../../rtl/boards/tinyfpga_bx/clock_pll.v,../../../../rtl/cpu/arlet_6502.v,../../../../rtl/cpu/arlet/ALU.v,../../../../rtl/cpu/arlet/cpu.v,../../../../rtl/ps2keyboard/debounce.v,../../../../rtl/ps2keyboard/ps2keyboard.v,../../../../rtl/uart/async_tx_rx.v,../../../../rtl/uart/uart.v,../../../../rtl/vga/font_rom.v,../../../../rtl/vga/vga.v,../../../../rtl/vga/vram.v
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ProjectCFiles=
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CurImplementation=icecube2_Implmnt
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Implementations=icecube2_Implmnt
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StartFromSynthesis=yes
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IPGeneration=false
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[icecube2_Implmnt]
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DeviceFamily=iCE40
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Device=LP8K
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DevicePackage=CM81
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DevicePower=
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NetlistFile=icecube2_Implmnt/icecube2.edf
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AdditionalEDIFFile=
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IPEDIFFile=
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DesignLib=icecube2_Implmnt/sbt/netlist/oadb-apple1_top
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DesignView=_rt
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DesignCell=apple1_top
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SynthesisSDCFile=icecube2_Implmnt/icecube2.scf
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UserPinConstraintFile=
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UserSDCFile=
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PhysicalConstraintFile=../tinyfpga_bx.pcf
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BackendImplPathName=
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Devicevoltage=1.14
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DevicevoltagePerformance=+/-5%(datasheet default)
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DeviceTemperature=85
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TimingAnalysisBasedOn=Worst
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OperationRange=Commercial
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TypicalCustomTemperature=25
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WorstCustomTemperature=85
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BestCustomTemperature=0
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IOBankVoltages=topBank,3.3 bottomBank,3.3 leftBank,3.3 rightBank,3.3
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derValue=1.03369
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TimingPathNumberStick=0
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[lse options]
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CarryChain=True
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CarryChainLength=0
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CommandLineOptions=
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EBRUtilization=100.00
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FSMEncodingStyle=Auto
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FixGatedClocks=True
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I/OInsertion=True
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IntermediateFileDump=False
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LoopLimit=1950
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MaximalFanout=10000
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MemoryInitialValueFileSearchPath=
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NumberOfCriticalPaths=3
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OptimizationGoal=Area
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PropagateConstants=True
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RAMStyle=Auto
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ROMStyle=Auto
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RWCheckOnRam=False
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RemoveDuplicateRegisters=True
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ResolvedMixedDrivers=False
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ResourceSharing=True
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TargetFrequency=
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TopLevelUnit=
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UseIORegister=Auto
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VHDL2008=False
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VerilogIncludeSearchPath=
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[tool options]
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PlacerEffortLevel=std
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PlacerAutoLutCascade=yes
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PlacerAutoRamCascade=yes
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PlacerPowerDriven=no
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PlacerAreaDriven=no
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RouteWithTimingDriven=yes
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RouteWithPinPermutation=yes
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BitmapSPIFlashMode=yes
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BitmapRAM4KInit=yes
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BitmapInitRamBank=1111
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BitmapOscillatorFR=low
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BitmapEnableWarmBoot=yes
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BitmapDisableHeader=no
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BitmapSetSecurity=no
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BitmapSetNoUsedIONoPullup=no
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FloorPlannerShowFanInNets=yes
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FloorPlannerShowFanOutNets=yes
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HookTo3rdPartyTextEditor=
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