39 lines
1.5 KiB
Verilog
39 lines
1.5 KiB
Verilog
module clock_pll(REFERENCECLK,
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PLLOUTCORE,
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PLLOUTGLOBAL,
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RESET);
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input REFERENCECLK;
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input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */
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output PLLOUTCORE;
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output PLLOUTGLOBAL;
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SB_PLL40_CORE clock_pll_inst(.REFERENCECLK(REFERENCECLK),
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.PLLOUTCORE(PLLOUTCORE),
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.PLLOUTGLOBAL(PLLOUTGLOBAL),
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.EXTFEEDBACK(1'd0),
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.DYNAMICDELAY(8'd0),
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.RESETB(RESET),
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.BYPASS(1'b0),
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.LATCHINPUTVALUE(1'd0),
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.LOCK(),
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.SDI(1'd0),
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.SDO(),
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.SCLK(1'd0));
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//\\ Fin=16, Fout=25;
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defparam clock_pll_inst.DIVR = 4'b0000;
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defparam clock_pll_inst.DIVF = 7'b0110001;
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defparam clock_pll_inst.DIVQ = 3'b101;
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defparam clock_pll_inst.FILTER_RANGE = 3'b001;
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defparam clock_pll_inst.FEEDBACK_PATH = "SIMPLE";
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defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
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defparam clock_pll_inst.FDA_FEEDBACK = 4'b0000;
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defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
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defparam clock_pll_inst.FDA_RELATIVE = 4'b0000;
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defparam clock_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
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defparam clock_pll_inst.PLLOUT_SELECT = "GENCLK";
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defparam clock_pll_inst.ENABLE_ICEGATE = 1'b0;
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endmodule
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