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46 lines
1.4 KiB
Verilog
46 lines
1.4 KiB
Verilog
// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Wrapper for Apple Integer Basic ROM
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//
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// Author.....: Alan Garfield
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// Niels A. Moseley
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// Date.......: 26-1-2018
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//
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module rom_basic(
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input clk, // clock signal
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input [11:0] address, // address bus
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output reg [7:0] dout // 8-bit data bus (output)
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);
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`ifdef SIM
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parameter BASIC_FILENAME = "../roms/basic.hex";
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`else
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parameter BASIC_FILENAME = "../../roms/basic.hex";
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`endif
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reg [7:0] rom_data[0:4095];
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initial
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$readmemh(BASIC_FILENAME, rom_data, 0, 4095);
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always @(posedge clk)
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dout <= rom_data[address];
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endmodule
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