Apple-1-HW/verilog-apple-one
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verilog-apple-one/rtl/boards
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Olof Kindgren 3a330aeccb Remove non-existing port assignments
2018-02-12 15:19:40 +01:00
..
ice40hx8k-b-evn Expose ROM/RAM files as top-level parameters 2018-02-12 14:04:00 +01:00
terasic_de0 Expose ROM/RAM files as top-level parameters 2018-02-12 14:04:00 +01:00
tinyfpga_b2 Remove non-existing port assignments 2018-02-12 15:19:40 +01:00
upduino Expose ROM/RAM files as top-level parameters 2018-02-12 14:04:00 +01:00