Apple-1-HW/verilog-apple-one
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verilog-apple-one/rtl/boards/ice40hx8k-b-evn
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Olof Kindgren 2226afe669 Expose ROM/RAM files as top-level parameters 
This allows file names to be overridden at compile-time.

It also gets rid of the ifdef SIM in the verilog components
2018-02-12 14:04:00 +01:00
..
apple1_hx8k.v Expose ROM/RAM files as top-level parameters 2018-02-12 14:04:00 +01:00
clock_pll_inst.v moved tinyfpga rtl to rtl/boards 2018-02-12 08:43:29 +11:00
clock_pll_v.lpc moved tinyfpga rtl to rtl/boards 2018-02-12 08:43:29 +11:00
clock_pll.v moved tinyfpga rtl to rtl/boards 2018-02-12 08:43:29 +11:00