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77 lines
2.4 KiB
Verilog
77 lines
2.4 KiB
Verilog
// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: 7-segment display driver for DE0 board
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//
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// Author.....: Niels A. Moseley
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// Date.......: 26-1-2018
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//
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module segmentdisplay (
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clk,
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latch,
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hexdigit_in,
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display_out
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);
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input clk,latch;
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input [3:0] hexdigit_in;
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output reg [0:6] display_out;
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always @(posedge clk)
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begin
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if (latch == 1)
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begin
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case (hexdigit_in)
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4'b0000:
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display_out <= 7'b1000000;
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4'b0001:
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display_out <= 7'b1111001;
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4'b0010:
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display_out <= 7'b0100100;
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4'b0011:
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display_out <= 7'b0110000;
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4'b0100:
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display_out <= 7'b0011001;
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4'b0101:
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display_out <= 7'b0010010;
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4'b0110:
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display_out <= 7'b0000010;
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4'b0111:
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display_out <= 7'b1111000;
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4'b1000:
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display_out <= 7'b0000000;
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4'b1001:
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display_out <= 7'b0011000;
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4'b1010:
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display_out <= 7'b0001000;
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4'b1011:
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display_out <= 7'b0000011;
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4'b1100:
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display_out <= 7'b1000110;
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4'b1101:
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display_out <= 7'b0100001;
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4'b1110:
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display_out <= 7'b0000110;
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4'b1111:
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display_out <= 7'b0001110;
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endcase
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end
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end
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endmodule
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