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Apple-1-HW
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verilog-apple-one
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https://github.com/alangarf/apple-one.git
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verilog-apple-one
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rtl
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vga
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Alan Garfield
7b3c65b8d9
Fixed issue with yosys compile
2018-02-05 00:24:12 +11:00
..
font_rom.v
wip of the pipeline VGA module. stupid yosys bug, but testbench looks ok
2018-02-05 00:12:06 +11:00
vga.v
Fixed issue with yosys compile
2018-02-05 00:24:12 +11:00
vram.v
Fixed issue with yosys compile
2018-02-05 00:24:12 +11:00