mirror of
https://github.com/alangarf/apple-one.git
synced 2024-06-02 04:41:26 +00:00
65 lines
1.8 KiB
Plaintext
65 lines
1.8 KiB
Plaintext
#-- Synopsys, Inc.
|
|
#-- Project file C:\Users\Alan\Documents\GitHub\apple-one\boards\ice40hx8k\appleone\appleone_syn.prj
|
|
#project files
|
|
|
|
add_file -verilog -lib work "../../../rtl/apple1_top.v"
|
|
add_file -verilog -lib work "../../../rtl/boards/ice40hx8k/clocks.v"
|
|
add_file -verilog -lib work "../../../rtl/boards/ice40hx8k/clock_pll.v"
|
|
add_file -verilog -lib work "../../../rtl/cpu/ALU.v"
|
|
add_file -verilog -lib work "../../../rtl/cpu/cpu.v"
|
|
add_file -verilog -lib work "../../../rtl/rom_wozmon.v"
|
|
add_file -verilog -lib work "../../../rtl/uart/uart.v"
|
|
add_file -verilog -lib work "../../../rtl/ram.v"
|
|
add_file -constraint -lib work "appleone_syn.sdc"
|
|
#implementation: "appleone_Implmnt"
|
|
impl -add appleone_Implmnt -type fpga
|
|
|
|
#implementation attributes
|
|
set_option -vlog_std v2001
|
|
set_option -project_relative_includes 1
|
|
|
|
#device options
|
|
set_option -technology SBTiCE40
|
|
set_option -part iCE40HX8K
|
|
set_option -package CT256
|
|
set_option -speed_grade
|
|
set_option -part_companion ""
|
|
|
|
#compilation/mapping options
|
|
|
|
# mapper_options
|
|
set_option -frequency auto
|
|
set_option -write_verilog 0
|
|
set_option -write_vhdl 0
|
|
|
|
# Silicon Blue iCE40
|
|
set_option -maxfan 10000
|
|
set_option -disable_io_insertion 0
|
|
set_option -pipe 1
|
|
set_option -retiming 0
|
|
set_option -update_models_cp 0
|
|
set_option -fixgatedclocks 2
|
|
set_option -fixgeneratedclocks 0
|
|
|
|
# NFilter
|
|
set_option -popfeed 0
|
|
set_option -constprop 0
|
|
set_option -createhierarchy 0
|
|
|
|
# sequential_optimization_options
|
|
set_option -symbolic_fsm_compiler 1
|
|
|
|
# Compiler Options
|
|
set_option -compiler_compatible 0
|
|
set_option -resource_sharing 1
|
|
|
|
#automatic place and route (vendor) options
|
|
set_option -write_apr_constraint 1
|
|
|
|
#set result format/file last
|
|
project -result_format "edif"
|
|
project -result_file ./appleone_Implmnt/appleone.edf
|
|
project -log_file "./appleone_Implmnt/appleone.srr"
|
|
impl -active appleone_Implmnt
|
|
project -run synthesis -clean
|