mirror of
https://github.com/alangarf/apple-one.git
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70 lines
2.2 KiB
Verilog
70 lines
2.2 KiB
Verilog
// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Apple 1 implementation for the iCE40HX8K dev
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// board.
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//
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// Author.....: Alan Garfield
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// Date.......: 26-1-2018
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//
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module apple1_top(
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input clk, // 100 MHz board clock
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// I/O interface to computer
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input uart_rx, // asynchronous serial data input from computer
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output uart_tx, // asynchronous serial data output to computer
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output uart_cts, // clear to send flag to computer
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// Outputs to VGA display
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output vga_h_sync, // hozizontal VGA sync pulse
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output vga_v_sync, // vertical VGA sync pulse
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output [2:0] vga_r, // red VGA signal
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output [2:0] vga_g, // green VGA signal
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output [2:0] vga_b, // blue VGA signal
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input [1:0] button
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);
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wire clk25;
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pll pll(.clock_in(clk),
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.clock_out(clk25),
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);
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wire vga_bit;
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// set the monochrome base colour here..
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assign vga_r[2:0] = vga_bit ? 3'b100 : 3'b000;
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assign vga_g[2:0] = vga_bit ? 3'b111 : 3'b000;
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assign vga_b[2:0] = vga_bit ? 3'b100 : 3'b000;
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// apple one main system
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apple1 my_apple1(
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.clk25(clk25),
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.rst_n(button[0]),
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.uart_rx(uart_rx),
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.uart_tx(uart_tx),
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.uart_cts(uart_cts),
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.clr_screen_btn(0),
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.vga_h_sync(vga_h_sync),
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.vga_v_sync(vga_v_sync),
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.vga_red(vga_bit),
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.ps2_select(1'b0),
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);
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endmodule
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