Apple-1-HW/verilog-apple-one
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verilog-apple-one/tools/iverilog
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Olof Kindgren 2226afe669 Expose ROM/RAM files as top-level parameters 
This allows file names to be overridden at compile-time.

It also gets rid of the ifdef SIM in the verilog components
2018-02-12 14:04:00 +01:00
..
apple1_files.txt
Moved test benches to tools
2018-02-12 07:02:41 +11:00
apple1_tb.v
Expose ROM/RAM files as top-level parameters
2018-02-12 14:04:00 +01:00
run_testbench.bat
Moved test benches to tools
2018-02-12 07:02:41 +11:00
run_vga_tb.sh
Moved test benches to tools
2018-02-12 07:02:41 +11:00
vga_files.txt
Moved test benches to tools
2018-02-12 07:02:41 +11:00
vga_tb.v
Moved test benches to tools
2018-02-12 07:02:41 +11:00