322 lines
8.0 KiB
Verilog
322 lines
8.0 KiB
Verilog
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// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Top level test bench for apple1_top
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//
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// Author.....: Niels A. Moseley
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// Date.......: 26-1-2018
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//
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`timescale 1ns/100ps
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module ukp_tb;
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reg clk25;
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reg clkusb;
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reg rst;
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reg [3:0] kbd_adr;
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wire usb_dm_out, usb_dp_out;
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reg usb_dm_in, usb_dp_in;
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wire record_n;
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wire [7:0] kbd_data;
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//////////////////////////////////////////////////////////////////////////
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// Setup dumping of data for inspection
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initial begin
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clk25 = 1'b0;
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clkusb = 1'b0;
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usb_dm_in = 1'b1;
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usb_dp_in = 1'b0;
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kbd_adr = 1'b0;
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rst = 1'b1;
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$display("Starting...");
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$dumpfile("ukp_tb.vcd");
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$dumpvars;
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#5
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rst = 1'b0;
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// switch off drive to allow seeing bus reset, real USB bus would have
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// pull downs and device would have stronger pull up on the D- pin. To
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// reset bus host yanks both D+ and D- to ground, in verilog hiz only
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// way to see that. It's not real, but useful to see
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#6097910.3
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usb_dm_in = 1'b0; // K -- SYNC
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1; // J
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0; // K
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1; // J
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0; // K
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1; // J
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0; // K
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b0; // K --
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1; // J -- ACK 0
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b1; // J 1
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0; // K 0
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1; // J 0
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b1; // J 1
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0; // K 0
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b0; // K 1
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b0; // K -- 1
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b0; // -- SE0
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0; // -- SE0
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b1; // J
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b1; // J
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usb_dp_in = 1'b0;
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#33776.2
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usb_dm_in = 1'b0; // K -- SYNC
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1; // J
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0; // K
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1; // J
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0; // K
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1; // J
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0; // K
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b0; // K --
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1; // J -- NACK 0
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b1; // J 1
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0; // K 0
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b0; // J 1
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b0; // J 1
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1; // K 0
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b1; // K 1
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0; // K -- 0
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b0; // -- SE0
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0; // -- SE0
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b1; // J
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b1; // J
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usb_dp_in = 1'b0;
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#33776.2
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usb_dm_in = 1'b0; // K -- SYNC
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1; // J
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0; // K
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1; // J
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0; // K
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1; // J
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0; // K
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b0; // K --
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b0; // K -- DATA0 1
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b0; // K 1
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1; // J 0
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b1; // J 1
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0; // K 0
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1; // K 0
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b1; // K 1
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0; // K -- 0
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1; // -- CRC
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0;
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1;
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0;
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1;
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0;
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1;
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0;
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1;
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0;
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1;
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0;
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1;
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0;
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b1;
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0;
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usb_dp_in = 1'b1;
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#667.2
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usb_dm_in = 1'b0; // -- SE0
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b0; // -- SE0
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b1; // J
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usb_dp_in = 1'b0;
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#667.2
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usb_dm_in = 1'b1; // J
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usb_dp_in = 1'b0;
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#1500000 $display("Stopping...");
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$finish;
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end
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//////////////////////////////////////////////////////////////////////////
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// Clock
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//
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always
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#20 clk25 = !clk25;
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always
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#41.665 clkusb <= !clkusb;
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//////////////////////////////////////////////////////////////////////////
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// Core of system
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ukp my_ukp (
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.clk25(clk25),
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.clkusb(clkusb),
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.rst(rst),
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.usb_dm_in(usb_dm_in),
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.usb_dp_in(usb_dp_in),
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.usb_dm_out(usb_dm_out),
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.usb_dp_out(usb_dp_out),
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.record_n(record_n),
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.kbd_adr(kbd_adr),
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.kbd_data(kbd_data)
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);
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endmodule
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