95 lines
2.3 KiB
Verilog
95 lines
2.3 KiB
Verilog
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// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Top level test bench for apple1_top
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//
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// Author.....: Niels A. Moseley
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// Date.......: 26-1-2018
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//
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`timescale 1ns/1ps
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module vga_tb;
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reg clk25, rst, address, w_en, blink_clken;
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reg [7:0] din;
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wire vga_h_sync, vga_v_sync, vga_red, vga_grn, vga_blu;
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//////////////////////////////////////////////////////////////////////////
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// Setup dumping of data for inspection
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initial begin
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clk25 = 1'b0;
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rst = 1'b0;
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address = 1'b0;
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w_en = 1'b0;
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blink_clken = 1'b0;
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din = 8'd0;
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#5
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rst = 1'b1;
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#5
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rst = 1'b0;
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$display("Starting...");
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$dumpfile("vga_tb.vcd");
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$dumpvars;
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//#180000
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//uart_rx = 1'b0;
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//#400
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//uart_rx = 1'b1;
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//#400
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//uart_rx = 1'b0;
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//#400
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//uart_rx = 1'b1;
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//#800
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//uart_rx = 1'b0;
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//#1600
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//uart_rx = 1'b1;
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#50000000 $display("Stopping...");
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$finish;
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end
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//////////////////////////////////////////////////////////////////////////
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// Clock
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always
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#20 clk25 = !clk25;
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//////////////////////////////////////////////////////////////////////////
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// Core of system
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vga my_vga (
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.clk25(clk25),
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.enable(1'b1),
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.rst(rst),
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.vga_h_sync(vga_h_sync),
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.vga_v_sync(vga_v_sync),
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.vga_red(vga_red),
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.vga_grn(vga_grn),
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.vga_blu(vga_blu),
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.address(address),
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.w_en(w_en),
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.din(din)
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);
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endmodule
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