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16 lines
602 B
Verilog
16 lines
602 B
Verilog
module Flag_CrossDomain(
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input clkA,
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input FlagIn_clkA, // this is a one-clock pulse from the clkA domain
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input clkB,
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output FlagOut_clkB // from which we generate a one-clock pulse in clkB domain
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);
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reg FlagToggle_clkA;
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always @(posedge clkA) FlagToggle_clkA <= FlagToggle_clkA ^ FlagIn_clkA; // when flag is asserted, this signal toggles (clkA domain)
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reg [2:0] SyncA_clkB;
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always @(posedge clkB) SyncA_clkB <= {SyncA_clkB[1:0], FlagToggle_clkA}; // now we cross the clock domains
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assign FlagOut_clkB = (SyncA_clkB[2] ^ SyncA_clkB[1]); // and create the clkB flag
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endmodule
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