verilog-apple-one/boards at b42567e7592232ae9a16f5e73d6d3bd4cb9b7a5e - verilog-apple-one - Applefritter: Git

Apple-1-HW/verilog-apple-one

mirror of https://github.com/alangarf/apple-one.git synced 2025-08-07 15:25:53 +00:00

Files

History

Alan Garfield b42567e759 fiddled project files from icecube

2018-01-28 00:19:59 +11:00

..

fiddled project files from icecube

2018-01-28 00:19:59 +11:00

Added timing constraints and pin assignments to DE0 board. Integrated the 1MHz clock enable signal into the core top level. Top level now requires a 25MHz clock signal.

2018-01-26 22:38:46 +01:00