Apple-1-HW/verilog-apple-one
1
0
Fork 0
mirror of https://github.com/alangarf/apple-one.git synced 2024-11-19 21:31:08 +00:00
Code Issues Projects Releases Wiki Activity
bcaf9e6962
verilog-apple-one/boards/terasic_de0
History
Niels Moseley f067774293 Added timing constraints and pin assignments to DE0 board. Integrated the 1MHz clock enable signal into the core top level. Top level now requires a 25MHz clock signal.
2018-01-26 22:38:46 +01:00
..
apple-one.pin Disabled ice40 specific define and clock generation. Added Terasic DE0 Quartus files. 2018-01-26 21:29:12 +01:00
apple-one.qpf Disabled ice40 specific define and clock generation. Added Terasic DE0 Quartus files. 2018-01-26 21:29:12 +01:00
apple-one.qsf Added timing constraints and pin assignments to DE0 board. Integrated the 1MHz clock enable signal into the core top level. Top level now requires a 25MHz clock signal. 2018-01-26 22:38:46 +01:00