mirror of
https://github.com/alangarf/apple-one.git
synced 2024-11-19 21:31:08 +00:00
213 lines
8.8 KiB
Verilog
213 lines
8.8 KiB
Verilog
// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Top level test bench for apple1_top
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//
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// Author.....: Niels A. Moseley
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// Date.......: 26-1-2018
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//
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`timescale 1ns/1ps
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module apple1_tb;
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reg clk25, uart_rx, rst_n;
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wire uart_tx, uart_cts;
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//////////////////////////////////////////////////////////////////////////
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// Setup dumping of data for inspection
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initial begin
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force core_top.clk_div = 0;
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force core_top.cpu_clken = 0;
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force core_top.hard_reset = 0;
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force core_top.reset_cnt = 0;
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force core_top.my_cpu.arlet_cpu.AB = 0;
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force core_top.my_cpu.arlet_cpu.PC = 0;
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force core_top.my_cpu.arlet_cpu.ABL = 0;
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force core_top.my_cpu.arlet_cpu.ABH = 0;
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force core_top.my_cpu.arlet_cpu.DIHOLD = 0;
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force core_top.my_cpu.arlet_cpu.IRHOLD = 0;
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force core_top.my_cpu.arlet_cpu.IRHOLD_valid = 0;
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force core_top.my_cpu.arlet_cpu.C = 0;
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force core_top.my_cpu.arlet_cpu.Z = 0;
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force core_top.my_cpu.arlet_cpu.I = 0;
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force core_top.my_cpu.arlet_cpu.D = 0;
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force core_top.my_cpu.arlet_cpu.V = 0;
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force core_top.my_cpu.arlet_cpu.N = 0;
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force core_top.my_cpu.arlet_cpu.AI = 0;
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force core_top.my_cpu.arlet_cpu.BI = 0;
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force core_top.my_cpu.arlet_cpu.DO = 0;
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force core_top.my_cpu.arlet_cpu.WE = 0;
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force core_top.my_cpu.arlet_cpu.CI = 0;
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force core_top.my_cpu.arlet_cpu.NMI_edge = 0;
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force core_top.my_cpu.arlet_cpu.regsel = 0;
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force core_top.my_cpu.arlet_cpu.PC_inc = 0;
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force core_top.my_cpu.arlet_cpu.PC_temp = 0;
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force core_top.my_cpu.arlet_cpu.src_reg = 0;
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force core_top.my_cpu.arlet_cpu.dst_reg = 0;
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force core_top.my_cpu.arlet_cpu.index_y = 0;
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force core_top.my_cpu.arlet_cpu.load_reg = 0;
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force core_top.my_cpu.arlet_cpu.inc = 0;
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force core_top.my_cpu.arlet_cpu.write_back = 0;
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force core_top.my_cpu.arlet_cpu.load_only = 0;
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force core_top.my_cpu.arlet_cpu.store = 0;
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force core_top.my_cpu.arlet_cpu.adc_sbc = 0;
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force core_top.my_cpu.arlet_cpu.compare = 0;
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force core_top.my_cpu.arlet_cpu.shift = 0;
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force core_top.my_cpu.arlet_cpu.rotate = 0;
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force core_top.my_cpu.arlet_cpu.backwards = 0;
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force core_top.my_cpu.arlet_cpu.cond_true = 0;
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force core_top.my_cpu.arlet_cpu.cond_code = 0;
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force core_top.my_cpu.arlet_cpu.shift_right = 0;
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force core_top.my_cpu.arlet_cpu.alu_shift_right = 0;
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force core_top.my_cpu.arlet_cpu.op = 0;
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force core_top.my_cpu.arlet_cpu.alu_op = 0;
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force core_top.my_cpu.arlet_cpu.adc_bcd = 0;
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force core_top.my_cpu.arlet_cpu.adj_bcd = 0;
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force core_top.my_cpu.arlet_cpu.bit_ins = 0;
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force core_top.my_cpu.arlet_cpu.plp = 0;
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force core_top.my_cpu.arlet_cpu.php = 0;
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force core_top.my_cpu.arlet_cpu.clc = 0;
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force core_top.my_cpu.arlet_cpu.sed = 0;
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force core_top.my_cpu.arlet_cpu.cli = 0;
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force core_top.my_cpu.arlet_cpu.sei = 0;
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force core_top.my_cpu.arlet_cpu.clv = 0;
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force core_top.my_cpu.arlet_cpu.brk = 0;
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force core_top.my_cpu.arlet_cpu.res = 0;
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force core_top.my_cpu.arlet_cpu.write_register = 0;
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force core_top.my_cpu.arlet_cpu.ADJL = 0;
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force core_top.my_cpu.arlet_cpu.ADJH = 0;
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force core_top.my_cpu.arlet_cpu.NMI_1 = 0;
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force core_top.my_cpu.arlet_cpu.ALU.OUT = 0;
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force core_top.my_cpu.arlet_cpu.ALU.CO = 0;
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force core_top.my_cpu.arlet_cpu.ALU.N = 0;
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force core_top.my_cpu.arlet_cpu.ALU.HC = 0;
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force core_top.my_cpu.arlet_cpu.ALU.AI7 = 0;
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force core_top.my_cpu.arlet_cpu.ALU.BI7 = 0;
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force core_top.my_cpu.arlet_cpu.ALU.temp_logic = 0;
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force core_top.my_cpu.arlet_cpu.ALU.temp_BI = 0;
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force core_top.my_cpu.arlet_cpu.ALU.temp_l = 0;
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force core_top.my_cpu.arlet_cpu.ALU.temp_h = 0;
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clk25 = 1'b0;
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uart_rx = 1'b0;
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rst_n = 1'b0;
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#40 rst_n = 1'b1;
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release core_top.clk_div;
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release core_top.cpu_clken;
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release core_top.hard_reset;
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release core_top.reset_cnt;
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release core_top.my_cpu.arlet_cpu.AB;
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release core_top.my_cpu.arlet_cpu.PC;
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release core_top.my_cpu.arlet_cpu.ABL;
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release core_top.my_cpu.arlet_cpu.ABH;
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release core_top.my_cpu.arlet_cpu.DIHOLD;
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release core_top.my_cpu.arlet_cpu.IRHOLD;
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release core_top.my_cpu.arlet_cpu.IRHOLD_valid;
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release core_top.my_cpu.arlet_cpu.C;
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release core_top.my_cpu.arlet_cpu.Z;
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release core_top.my_cpu.arlet_cpu.I;
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release core_top.my_cpu.arlet_cpu.D;
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release core_top.my_cpu.arlet_cpu.V;
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release core_top.my_cpu.arlet_cpu.N;
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release core_top.my_cpu.arlet_cpu.AI;
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release core_top.my_cpu.arlet_cpu.BI;
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release core_top.my_cpu.arlet_cpu.DO;
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release core_top.my_cpu.arlet_cpu.WE;
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release core_top.my_cpu.arlet_cpu.CI;
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release core_top.my_cpu.arlet_cpu.NMI_edge;
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release core_top.my_cpu.arlet_cpu.regsel;
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release core_top.my_cpu.arlet_cpu.PC_inc;
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release core_top.my_cpu.arlet_cpu.PC_temp;
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release core_top.my_cpu.arlet_cpu.src_reg;
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release core_top.my_cpu.arlet_cpu.dst_reg;
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release core_top.my_cpu.arlet_cpu.index_y;
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release core_top.my_cpu.arlet_cpu.load_reg;
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release core_top.my_cpu.arlet_cpu.inc;
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release core_top.my_cpu.arlet_cpu.write_back;
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release core_top.my_cpu.arlet_cpu.load_only;
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release core_top.my_cpu.arlet_cpu.store;
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release core_top.my_cpu.arlet_cpu.adc_sbc;
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release core_top.my_cpu.arlet_cpu.compare;
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release core_top.my_cpu.arlet_cpu.shift;
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release core_top.my_cpu.arlet_cpu.rotate;
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release core_top.my_cpu.arlet_cpu.backwards;
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release core_top.my_cpu.arlet_cpu.cond_true;
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release core_top.my_cpu.arlet_cpu.cond_code;
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release core_top.my_cpu.arlet_cpu.shift_right;
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release core_top.my_cpu.arlet_cpu.alu_shift_right;
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release core_top.my_cpu.arlet_cpu.op;
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release core_top.my_cpu.arlet_cpu.alu_op;
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release core_top.my_cpu.arlet_cpu.adc_bcd;
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release core_top.my_cpu.arlet_cpu.adj_bcd;
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release core_top.my_cpu.arlet_cpu.bit_ins;
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release core_top.my_cpu.arlet_cpu.plp;
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release core_top.my_cpu.arlet_cpu.php;
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release core_top.my_cpu.arlet_cpu.clc;
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release core_top.my_cpu.arlet_cpu.sec;
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release core_top.my_cpu.arlet_cpu.cld;
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release core_top.my_cpu.arlet_cpu.sed;
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release core_top.my_cpu.arlet_cpu.sei;
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release core_top.my_cpu.arlet_cpu.clv;
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release core_top.my_cpu.arlet_cpu.brk;
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release core_top.my_cpu.arlet_cpu.res;
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release core_top.my_cpu.arlet_cpu.write_register;
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release core_top.my_cpu.arlet_cpu.ADJL;
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release core_top.my_cpu.arlet_cpu.ADJH;
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release core_top.my_cpu.arlet_cpu.NMI_1;
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release core_top.my_cpu.arlet_cpu.ALU.OUT;
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release core_top.my_cpu.arlet_cpu.ALU.CO;
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release core_top.my_cpu.arlet_cpu.ALU.N;
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release core_top.my_cpu.arlet_cpu.ALU.HC;
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release core_top.my_cpu.arlet_cpu.ALU.AI7;
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release core_top.my_cpu.arlet_cpu.ALU.BI7;
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release core_top.my_cpu.arlet_cpu.ALU.temp_logic;
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release core_top.my_cpu.arlet_cpu.ALU.temp_BI;
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release core_top.my_cpu.arlet_cpu.ALU.temp_l;
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release core_top.my_cpu.arlet_cpu.ALU.temp_h;
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$display("Starting...");
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$dumpfile("apple1_top_tb.vcd");
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$dumpvars;
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#1000000 $display("Stopping...");
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$finish;
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end
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//////////////////////////////////////////////////////////////////////////
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// Clock
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always
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#20 clk25 = !clk25;
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//////////////////////////////////////////////////////////////////////////
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// Core of system
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apple1 #(
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"../roms/ram.hex",
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"../roms/wozmon.hex"
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) core_top (
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.clk25(clk25),
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.rst_n(rst_n),
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.uart_rx(uart_rx),
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.uart_tx(uart_tx),
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.uart_cts(uart_cts)
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);
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endmodule
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