verilog-apple-one/boards at c4d42fae3c91212f57f3083646268ced87092ae2 - verilog-apple-one - Applefritter: Git

Apple-1-HW/verilog-apple-one

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Alan Garfield c4d42fae3c fixed testbench and split CPU cores

2018-01-27 17:00:33 +11:00

..

fixed testbench and split CPU cores

2018-01-27 17:00:33 +11:00

Added timing constraints and pin assignments to DE0 board. Integrated the 1MHz clock enable signal into the core top level. Top level now requires a 25MHz clock signal.

2018-01-26 22:38:46 +01:00