mirror of
https://github.com/alangarf/apple-one.git
synced 2024-10-15 09:23:42 +00:00
11 lines
177 B
Verilog
11 lines
177 B
Verilog
module MUX #(
|
|
parameter N=1
|
|
) (
|
|
output wire o,
|
|
input wire i,
|
|
input wire [N-1:0] s,
|
|
input wire [N-1:0] d);
|
|
|
|
assign o = (|s) ? &(d|(~s)) : i;
|
|
endmodule
|