mirror of
https://github.com/alangarf/apple-one.git
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110 lines
3.1 KiB
Verilog
110 lines
3.1 KiB
Verilog
// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Top level Apple 1 module for Terasic DE0 board
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//
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// Author.....: Niels A. Moseley
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// Date.......: 26-1-2018
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//
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module apple1_de0_top(
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input CLOCK_50, // the 50 MHz DE0 master clock
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// UART I/O signals
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output UART_TXD, // UART transmit pin on DE0 board
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input UART_RXD, // UART receive pin on DE0 board
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output UART_CTS, // UART clear-to-send pin on DE0 board
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output [7:0] LEDG, // monitoring for lower 8 address bits
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input [2:0] BUTTON, // BUTTON[0] for reset
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output [6:0] HEX0_D,
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output [6:0] HEX1_D,
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output [6:0] HEX2_D,
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output [6:0] HEX3_D,
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input PS2_KBCLK,
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input PS2_KBDAT
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);
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//////////////////////////////////////////////////////////////////////////
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// Registers and Wires
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reg clk25;
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wire [15:0] pc_monitor;
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// generate 25MHz clock from 50MHz master clock
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always @(posedge CLOCK_50)
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begin
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clk25 <= ~clk25;
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end
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//////////////////////////////////////////////////////////////////////////
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// Core of system
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apple1 apple1_top(
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.clk25(clk25),
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.rst_n(BUTTON[0]), // we don't have any reset pulse..
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.uart_rx(UART_RXD),
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.uart_tx(UART_TXD),
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.uart_cts(UART_CTS),
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.pc_monitor(pc_monitor)
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);
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//////////////////////////////////////////////////////////////////////////
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// Display 6502 address on 7-segment displays
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segmentdisplay seg1(
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.clk(clk25),
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.latch(1'b1),
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.hexdigit_in(pc_monitor[3:0]),
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.display_out(HEX0_D)
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);
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segmentdisplay seg2(
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.clk(clk25),
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.latch(1'b1),
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.hexdigit_in(pc_monitor[7:4]),
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.display_out(HEX1_D)
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);
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segmentdisplay seg3(
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.clk(clk25),
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.latch(1'b1),
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.hexdigit_in(pc_monitor[11:8]),
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.display_out(HEX2_D)
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);
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segmentdisplay seg4(
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.clk(clk25),
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.latch(1'b1),
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.hexdigit_in(pc_monitor[15:12]),
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.display_out(HEX3_D)
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);
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//////////////////////////////////////////////////////////////////////////
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// Experimental PS/2 interface
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ps2keyboard keys(
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.clk25(clk25),
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.reset(~BUTTON[0]),
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.key_clk(PS2_KBCLK),
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.key_din(PS2_KBDAT),
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.cs(1'b1),
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.address(1'b0),
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.dout(LEDG[7:0])
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);
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endmodule
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