verilog-apple-one/boards at e9ff2b294e22cb00fbfbc6ffa633a6dfee8e2041 - verilog-apple-one - Applefritter: Git

Apple-1-HW/verilog-apple-one

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Alan Garfield e9ff2b294e more project file fiddles by the tool. :/

2018-01-28 00:23:43 +11:00

..

more project file fiddles by the tool. :/

2018-01-28 00:23:43 +11:00

Added timing constraints and pin assignments to DE0 board. Integrated the 1MHz clock enable signal into the core top level. Top level now requires a 25MHz clock signal.

2018-01-26 22:38:46 +01:00