verilog-apple-one/boards at f06777429371e11f1dba21b5d5d99cfd1401dbf0 - verilog-apple-one - Applefritter: Git

Apple-1-HW/verilog-apple-one

mirror of https://github.com/alangarf/apple-one.git synced 2025-08-07 15:25:53 +00:00

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History

Niels Moseley f067774293 Added timing constraints and pin assignments to DE0 board. Integrated the 1MHz clock enable signal into the core top level. Top level now requires a 25MHz clock signal.

2018-01-26 22:38:46 +01:00

..

ice40hx8k/appleone

move things around.

2018-01-27 00:21:05 +11:00

Added timing constraints and pin assignments to DE0 board. Integrated the 1MHz clock enable signal into the core top level. Top level now requires a 25MHz clock signal.

2018-01-26 22:38:46 +01:00