AppleIISd/VHDL/AppleIISd_Test.vhd

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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
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-- Create Date: 00:42:59 10/10/2017
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-- Design Name:
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-- Module Name: U:/AppleIISd/VHDL/IO_Test.vhd
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-- Project Name: AppleIISd
-- Target Device:
-- Tool versions:
-- Description:
--
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-- VHDL Test Bench Created by ISE for module: IO
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--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY AppleIISd_Test IS
END AppleIISd_Test;
ARCHITECTURE behavior OF AppleIISd_Test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT AppleIISd
PORT(
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ADD_HIGH : IN std_logic_vector(11 downto 8);
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ADD_LOW : IN std_logic_vector(1 downto 0);
B : OUT std_logic_vector(10 downto 8);
CARD : IN std_logic;
DATA : INOUT std_logic_vector(7 downto 0);
CLK : IN std_logic;
LED : OUT std_logic;
NDEV_SEL : IN std_logic;
NG : OUT std_logic;
NIO_SEL : IN std_logic;
NIO_STB : IN std_logic;
NOE : OUT std_logic;
PHI0 : IN std_logic;
NRESET : IN std_logic;
RNW : IN std_logic;
MISO : IN std_logic;
MOSI : OUT std_logic;
NSEL : OUT std_logic;
SCLK : OUT std_logic;
WP : IN std_logic;
data_dbg : out std_logic_vector (7 downto 0);
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add_dbg : out std_logic_vector (1 downto 0);
data_en_dbg : out std_logic
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);
END COMPONENT;
--Inputs
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signal ADD_HIGH : std_logic_vector(11 downto 8) := (others => '0');
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signal ADD_LOW : std_logic_vector(1 downto 0) := (others => 'U');
signal CARD : std_logic := '0';
signal CLK : std_logic := '0';
signal NDEV_SEL : std_logic := '1';
signal NIO_SEL : std_logic := '1';
signal NIO_STB : std_logic := '1';
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signal PHI0 : std_logic := '1';
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signal NRESET : std_logic := '1';
signal RNW : std_logic := '1';
signal MISO : std_logic := '1';
signal WP : std_logic := '0';
--BiDirs
signal DATA : std_logic_vector(7 downto 0) := (others => 'Z');
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--Outputs
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signal B : std_logic_vector(10 downto 8);
signal LED : std_logic;
signal NG : std_logic;
signal NOE : std_logic;
signal MOSI : std_logic;
signal NSEL : std_logic;
signal SCLK : std_logic;
signal data_dbg : std_logic_vector (7 downto 0);
signal add_dbg : std_logic_vector (1 downto 0);
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signal data_en_dbg : std_logic;
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-- Clock period definitions
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constant CLK_period : time := 142 ns;
-- Bus timings
-- worst case
constant ADD_valid : time := 300 ns; -- II+
constant DATA_valid : time := 200 ns; -- II+
constant ADD_hold : time := 15 ns; -- IIgs
--best case
--constant ADD_valid : time := 100 ns; -- IIgs
--constant DATA_valid : time := 30 ns; -- IIgs
--constant ADD_hold : time := 15 ns; -- IIgs
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BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: AppleIISd PORT MAP (
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ADD_HIGH => ADD_HIGH,
ADD_LOW => ADD_LOW,
B => B,
CARD => CARD,
DATA => DATA,
CLK => CLK,
LED => LED,
NDEV_SEL => NDEV_SEL,
NG => NG,
NIO_SEL => NIO_SEL,
NIO_STB => NIO_STB,
NOE => NOE,
PHI0 => PHI0,
NRESET => NRESET,
RNW => RNW,
MISO => MISO,
MOSI => MOSI,
NSEL => NSEL,
SCLK => SCLK,
WP => WP,
data_dbg => data_dbg,
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add_dbg => add_dbg,
data_en_dbg => data_en_dbg
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);
-- Clock process definitions
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CLK_process :process
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begin
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CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
PHI0_process :process(CLK)
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variable counter : integer range 0 to 7;
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begin
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if rising_edge(CLK) or falling_edge(CLK) then
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counter := counter + 1;
if counter = 7 then
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PHI0 <= not PHI0;
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counter := 0;
end if;
end if;
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end process;
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-- Stimulus process
stim_proc: process
begin
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-- hold reset state.
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wait for CLK_period * 10;
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NRESET <= '0';
wait for CLK_period * 20;
NRESET <= '1';
wait for CLK_period * 10;
DATA <= (others => 'Z');
ADD_LOW <= (others => 'U');
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-- read reg 3
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wait until falling_edge(PHI0);
wait for ADD_valid;
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ADD_LOW <= (others => '1');
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RNW <= '1';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
DATA <= (others => 'Z');
wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait for ADD_hold;
ADD_LOW <= (others => 'U');
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-- select card
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '1');
RNW <= '0';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
DATA <= (others => 'Z');
wait for DATA_valid;
DATA <= X"00";
wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait for ADD_hold;
--wait for CLK_period;
ADD_LOW <= (others => 'U');
RNW <= '1';
DATA <= (others => 'Z');
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-- send data
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wait until falling_edge(PHI0);
wait for ADD_valid;
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ADD_LOW <= (others => '0');
RNW <= '0';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
DATA <= (others => 'Z');
wait for DATA_valid;
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DATA <= X"AA";
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wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait for ADD_hold;
--wait for CLK_period;
ADD_LOW <= (others => 'U');
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RNW <= '1';
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DATA <= (others => 'Z');
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wait for 20 us;
-- deselect card
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '1');
RNW <= '0';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
DATA <= (others => 'Z');
wait for DATA_valid;
DATA <= X"01";
wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait for ADD_hold;
--wait for CLK_period;
ADD_LOW <= (others => 'U');
RNW <= '1';
DATA <= (others => 'Z');
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-- write ece
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= "01";
RNW <= '0';
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DATA <= (others => 'U');
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
DATA <= (others => 'Z');
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wait for DATA_valid;
DATA <= x"04";
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wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait for ADD_hold;
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--wait for CLK_period;
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ADD_LOW <= (others => 'U');
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RNW <= '1';
DATA <= (others => 'Z');
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-- send data
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '0');
RNW <= '0';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
DATA <= (others => 'Z');
wait for DATA_valid;
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DATA <= X"AA";
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wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait for ADD_hold;
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--wait for CLK_period;
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ADD_LOW <= (others => 'U');
RNW <= '1';
DATA <= (others => 'Z');
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-- read eprom low
wait for 3 us;
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '0');
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ADD_HIGH <= "0100"; -- must become "111"
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RNW <= '1';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NIO_SEL <= '0';
DATA <= (others => 'Z');
wait until falling_edge(PHI0);
NIO_SEL <= '1';
wait for ADD_hold;
ADD_LOW <= (others => 'U');
ADD_HIGH <= (others => 'U');
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-- read eprom high, selected
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wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '0');
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ADD_HIGH <= "1001"; -- must become "001"
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RNW <= '1';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NIO_STB <= '0';
DATA <= (others => 'Z');
wait until falling_edge(PHI0);
NIO_STB <= '1';
wait for ADD_hold;
ADD_LOW <= (others => 'U');
ADD_HIGH <= (others => 'U');
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-- read $CFFF
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '1');
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ADD_HIGH <= "1111";
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RNW <= '1';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NIO_STB <= '0';
DATA <= (others => 'Z');
wait until falling_edge(PHI0);
NIO_STB <= '1';
wait for ADD_hold;
ADD_LOW <= (others => 'U');
ADD_HIGH <= (others => 'U');
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-- read eprom high, deselected
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wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '0');
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ADD_HIGH <= "1101"; -- must become "101"
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RNW <= '1';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
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NIO_STB <= '0';
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DATA <= (others => 'Z');
wait until falling_edge(PHI0);
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NIO_STB <= '1';
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wait for ADD_hold;
ADD_LOW <= (others => 'U');
ADD_HIGH <= (others => 'U');
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wait;
end process;
END;