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Program enable added and verified
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@ -40,6 +40,7 @@ entity AddressDecoder is
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NIO_STB : in std_logic; -- $C800 - $CFFF, EEPROM banks 1 to 7
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NIO_STB : in std_logic; -- $C800 - $CFFF, EEPROM banks 1 to 7
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NRESET : in std_logic;
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NRESET : in std_logic;
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DATA_EN : out std_logic; -- to CPLD
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DATA_EN : out std_logic; -- to CPLD
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PGM_EN : in std_logic; -- from CPLD;
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NG : out std_logic; -- to bus transceiver
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NG : out std_logic; -- to bus transceiver
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NOE : out std_logic; -- to EEPROM
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NOE : out std_logic; -- to EEPROM
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NWE : out std_logic); -- to EEPROM
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NWE : out std_logic); -- to EEPROM
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@ -84,7 +85,8 @@ begin
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NWE <= RNW
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NWE <= RNW
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or (not NIO_SEL and not NIO_STB)
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or (not NIO_SEL and not NIO_STB)
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or (NIO_SEL and NIO_STB)
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or (NIO_SEL and NIO_STB)
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or (NIO_SEL and ncs);
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or (NIO_SEL and ncs)
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or not PGM_EN;
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cfxx <= a_int(8) and a_int(9) and a_int(10) and not nio_stb_int;
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cfxx <= a_int(8) and a_int(9) and a_int(10) and not nio_stb_int;
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@ -51,6 +51,7 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
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NIO_STB : IN std_logic;
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NIO_STB : IN std_logic;
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NRESET : IN std_logic;
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NRESET : IN std_logic;
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DATA_EN : OUT std_logic;
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DATA_EN : OUT std_logic;
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PGM_EN : IN std_logic;
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NG : OUT std_logic;
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NG : OUT std_logic;
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NOE : OUT std_logic;
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NOE : OUT std_logic;
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NWE : OUT std_logic
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NWE : OUT std_logic
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@ -67,6 +68,7 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
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signal NRESET : std_logic := '1';
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signal NRESET : std_logic := '1';
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signal CLK : std_logic := '0';
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signal CLK : std_logic := '0';
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signal PHI0 : std_logic := '1';
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signal PHI0 : std_logic := '1';
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signal PGM_EN : std_logic := '1';
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--Outputs
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--Outputs
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signal B : std_logic_vector(10 downto 8);
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signal B : std_logic_vector(10 downto 8);
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@ -92,6 +94,7 @@ BEGIN
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NIO_STB => NIO_STB,
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NIO_STB => NIO_STB,
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NRESET => NRESET,
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NRESET => NRESET,
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DATA_EN => DATA_EN,
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DATA_EN => DATA_EN,
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PGM_EN => PGM_EN,
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NG => NG,
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NG => NG,
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NOE => NOE,
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NOE => NOE,
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NWE => NWE
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NWE => NWE
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@ -175,11 +178,25 @@ BEGIN
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NIO_SEL <= '1';
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NIO_SEL <= '1';
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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-- CnXX access, write, select, no PGM_EN
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-- NG must be '0'
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-- NOE must be '1'
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-- NWE must be '1'
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RNW <= '0';
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PGM_EN <= '0';
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A <= "0100"; -- must become "000"
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wait until rising_edge(PHI0);
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NIO_SEL <= '0';
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wait until falling_edge(PHI0);
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NIO_SEL <= '1';
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wait until rising_edge(PHI0);
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-- C8xx access, selected
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-- C8xx access, selected
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-- NG must be '0'
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-- NG must be '0'
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-- NOE must be '0'
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-- NOE must be '0'
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-- NWE must be '1'
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-- NWE must be '1'
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RNW <= '1';
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RNW <= '1';
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PGM_EN <= '1';
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A <= "1000"; -- must become "001"
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A <= "1000"; -- must become "001"
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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NIO_STB <= '0';
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NIO_STB <= '0';
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File diff suppressed because it is too large
Load Diff
@ -70,6 +70,7 @@ architecture Behavioral of AppleIISd is
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signal addr_low_int : std_logic_vector (1 downto 0);
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signal addr_low_int : std_logic_vector (1 downto 0);
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signal data_en : std_logic;
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signal data_en : std_logic;
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signal pgm_en : std_logic;
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component SpiController is
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component SpiController is
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Port (
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Port (
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@ -87,7 +88,8 @@ Port (
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nsel : out std_logic;
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nsel : out std_logic;
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wp : in std_logic;
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wp : in std_logic;
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card : in std_logic;
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card : in std_logic;
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led : out std_logic
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led : out std_logic;
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pgm_en : out std_logic
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);
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);
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end component;
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end component;
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@ -103,6 +105,7 @@ Port (
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NIO_STB : in std_logic;
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NIO_STB : in std_logic;
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NRESET : in std_logic;
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NRESET : in std_logic;
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DATA_EN : out std_logic;
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DATA_EN : out std_logic;
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PGM_EN : in std_logic;
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NG : out std_logic;
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NG : out std_logic;
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NOE : out std_logic;
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NOE : out std_logic;
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NWE : out std_logic
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NWE : out std_logic
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@ -126,7 +129,8 @@ begin
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nsel => NSEL,
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nsel => NSEL,
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wp => WP,
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wp => WP,
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card => CARD,
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card => CARD,
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led => LED
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led => LED,
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pgm_en => pgm_en
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);
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);
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addDec: AddressDecoder port map(
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addDec: AddressDecoder port map(
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@ -140,6 +144,7 @@ begin
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NIO_STB => NIO_STB,
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NIO_STB => NIO_STB,
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NRESET => NRESET,
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NRESET => NRESET,
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DATA_EN => data_en,
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DATA_EN => data_en,
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PGM_EN => pgm_en,
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NOE => NOE,
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NOE => NOE,
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NWE => NWE,
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NWE => NWE,
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NG => NG
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NG => NG
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@ -25,6 +25,7 @@ Port (
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nsel : out STD_LOGIC;
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nsel : out STD_LOGIC;
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wp : in STD_LOGIC;
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wp : in STD_LOGIC;
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card : in STD_LOGIC;
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card : in STD_LOGIC;
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pgm_en : out STD_LOGIC;
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led : out STD_LOGIC
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led : out STD_LOGIC
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);
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);
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@ -40,6 +41,7 @@ architecture Behavioral of SpiController is
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signal spidataout: std_logic_vector (7 downto 0);
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signal spidataout: std_logic_vector (7 downto 0);
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signal sdhc: std_logic; -- is SDHC card
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signal sdhc: std_logic; -- is SDHC card
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signal inited: std_logic; -- card initialized
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signal inited: std_logic; -- card initialized
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signal pgmen: std_logic; -- enable EEPROM programming
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-- spi register flags
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-- spi register flags
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signal tc: std_logic; -- transmission complete; cleared on spi data read
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signal tc: std_logic; -- transmission complete; cleared on spi data read
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@ -66,7 +68,6 @@ architecture Behavioral of SpiController is
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signal shiftclk : std_logic;
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signal shiftclk : std_logic;
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begin
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begin
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--led <= not (inited);
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led <= not (bsy or not slavesel);
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led <= not (bsy or not slavesel);
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bsy <= start_shifting or shifting2;
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bsy <= start_shifting or shifting2;
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@ -194,6 +195,7 @@ begin
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-- outputs
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-- outputs
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nsel <= slavesel;
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nsel <= slavesel;
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pgm_en <= pgmen;
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tc_proc: process (ndev_sel, shiftdone)
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tc_proc: process (ndev_sel, shiftdone)
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begin
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begin
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@ -207,14 +209,14 @@ begin
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--------------------------
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--------------------------
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-- cpu register section
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-- cpu register section
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-- cpu read
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-- cpu read
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cpu_read: process(addr, spidatain, tc, bsy, frx,
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cpu_read: process(addr, spidatain, tc, bsy, frx, pgmen,
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ece, divisor, slavesel, wp, card, sdhc, inited)
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ece, divisor, slavesel, wp, card, sdhc, inited)
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begin
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begin
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case addr is
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case addr is
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when "00" => -- read SPI data in
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when "00" => -- read SPI data in
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data_out <= spidatain;
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data_out <= spidatain;
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when "01" => -- read status register
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when "01" => -- read status register
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data_out(0) <= '0';
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data_out(0) <= pgmen;
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data_out(1) <= '0';
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data_out(1) <= '0';
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data_out(2) <= ece;
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data_out(2) <= ece;
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data_out(3) <= '0';
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data_out(3) <= '0';
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@ -248,6 +250,7 @@ begin
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spidataout <= (others => '1');
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spidataout <= (others => '1');
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sdhc <= '0';
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sdhc <= '0';
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inited <= '0';
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inited <= '0';
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pgmen <= '0';
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elsif (card = '1') then
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elsif (card = '1') then
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sdhc <= '0';
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sdhc <= '0';
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inited <= '0';
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inited <= '0';
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@ -256,6 +259,7 @@ begin
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when "00" => -- write SPI data out (see other process above)
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when "00" => -- write SPI data out (see other process above)
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spidataout <= data_in;
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spidataout <= data_in;
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when "01" => -- write status register
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when "01" => -- write status register
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pgmen <= data_in(0);
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ece <= data_in(2);
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ece <= data_in(2);
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frx <= data_in(4);
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frx <= data_in(4);
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-- no bit 5 - 7
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-- no bit 5 - 7
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@ -273,4 +277,3 @@ begin
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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