From 596e7c3f1f0d4d4a7046822deaff85a55d5106f1 Mon Sep 17 00:00:00 2001
From: freitz85 <freitz85@gmail.com>
Date: Sun, 9 Jul 2017 13:28:18 +0200
Subject: [PATCH] Pin changes

---
 VHDL/AppleIISd.ucf | 14 +++++++-------
 VHDL/_pace.ucf     | 42 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 49 insertions(+), 7 deletions(-)
 create mode 100644 VHDL/_pace.ucf

diff --git a/VHDL/AppleIISd.ucf b/VHDL/AppleIISd.ucf
index 2c1aaa8..b6d0639 100644
--- a/VHDL/AppleIISd.ucf
+++ b/VHDL/AppleIISd.ucf
@@ -11,25 +11,25 @@ NET "b8"  LOC = "P26"  ;
 NET "b9"  LOC = "P27"  ;
 NET "card"  LOC = "P33"  ;
 NET "data<0>"  LOC = "P3"  ;
-NET "data<1>"  LOC = "P5"  ;
-NET "data<2>"  LOC = "P4"  ;
+NET "data<1>"  LOC = "P4"  ;
+NET "data<2>"  LOC = "P5"  ;
 NET "data<3>"  LOC = "P6"  ;
 NET "data<4>"  LOC = "P7"  ;
 NET "data<5>"  LOC = "P9"  ;
 NET "data<6>"  LOC = "P11"  ;
 NET "data<7>"  LOC = "P13"  ;
-NET "extclk"  LOC = "P42"  ;
+NET "extclk"  LOC = "P43"  ;
 NET "led"  LOC = "P29"  ;
 NET "ndev_sel"  LOC = "P24"  ;
 NET "ng"  LOC = "P12"  ;
 NET "nio_sel"  LOC = "P14"  ;
-NET "nio_stb"  LOC = "P40"  ;
-NET "nirq"  LOC = "P2"  ;
+NET "nio_stb"  LOC = "P42"  ;
+NET "nirq"  LOC = "P44"  ;
 NET "noe"  LOC = "P25"  ;
-NET "nphi2"  LOC = "P44"  ;
+NET "nphi2"  LOC = "P8"  ;
 NET "nreset"  LOC = "P20"  ;
 NET "nrw"  LOC = "P1"  ;
-NET "spi_miso"  LOC = "P43"  ;
+NET "spi_miso"  LOC = "P40"  ;
 NET "spi_mosi"  LOC = "P35"  ;
 NET "spi_Nsel"  LOC = "P28"  ;
 NET "spi_sclk"  LOC = "P34"  ;
diff --git a/VHDL/_pace.ucf b/VHDL/_pace.ucf
new file mode 100644
index 0000000..2c1aaa8
--- /dev/null
+++ b/VHDL/_pace.ucf
@@ -0,0 +1,42 @@
+#PACE: Start of Constraints generated by PACE
+
+#PACE: Start of PACE I/O Pin Assignments
+NET "a10"  LOC = "P38"  ;
+NET "a8"  LOC = "P36"  ;
+NET "a9"  LOC = "P37"  ;
+NET "addr<0>"  LOC = "P19"  ;
+NET "addr<1>"  LOC = "P18"  ;
+NET "b10"  LOC = "P22"  ;
+NET "b8"  LOC = "P26"  ;
+NET "b9"  LOC = "P27"  ;
+NET "card"  LOC = "P33"  ;
+NET "data<0>"  LOC = "P3"  ;
+NET "data<1>"  LOC = "P5"  ;
+NET "data<2>"  LOC = "P4"  ;
+NET "data<3>"  LOC = "P6"  ;
+NET "data<4>"  LOC = "P7"  ;
+NET "data<5>"  LOC = "P9"  ;
+NET "data<6>"  LOC = "P11"  ;
+NET "data<7>"  LOC = "P13"  ;
+NET "extclk"  LOC = "P42"  ;
+NET "led"  LOC = "P29"  ;
+NET "ndev_sel"  LOC = "P24"  ;
+NET "ng"  LOC = "P12"  ;
+NET "nio_sel"  LOC = "P14"  ;
+NET "nio_stb"  LOC = "P40"  ;
+NET "nirq"  LOC = "P2"  ;
+NET "noe"  LOC = "P25"  ;
+NET "nphi2"  LOC = "P44"  ;
+NET "nreset"  LOC = "P20"  ;
+NET "nrw"  LOC = "P1"  ;
+NET "spi_miso"  LOC = "P43"  ;
+NET "spi_mosi"  LOC = "P35"  ;
+NET "spi_Nsel"  LOC = "P28"  ;
+NET "spi_sclk"  LOC = "P34"  ;
+NET "wp"  LOC = "P39"  ;
+
+#PACE: Start of PACE Area Constraints
+
+#PACE: Start of PACE Prohibit Constraints
+
+#PACE: End of Constraints generated by PACE