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https://github.com/freitz85/AppleIISd.git
synced 2024-09-27 21:58:16 +00:00
Added waiting for card ready.
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BIN
AppleIISd.bin
BIN
AppleIISd.bin
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Images/Bus1.gif
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@ -13,9 +13,11 @@
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.import PRODOS
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.import SMARTPORT
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.import WRDATA
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.import GETR1
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.import GETR3
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.import SDCMD
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.import SDCMD0
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.import CARDDET
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.import READ
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@ -238,9 +240,7 @@ INIT: LDA #$03 ; set SPI mode 3
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LDY #10
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LDA #DUMMY
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@LOOP: STA DATA,X
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@WAIT: BIT CTRL,X
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BPL @WAIT
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@LOOP: JSR WRDATA
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DEY
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BNE @LOOP ; do 10 times
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LDA SS,X
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@ -251,7 +251,7 @@ INIT: LDA #$03 ; set SPI mode 3
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STA CMDLO
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LDA #>CMD0
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STA CMDHI
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JSR SDCMD
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JSR SDCMD0
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JSR GETR1 ; get response
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CMP #$01
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BNE @ERROR1 ; error!
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@ -261,6 +261,7 @@ INIT: LDA #$03 ; set SPI mode 3
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LDA #>CMD8
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STA CMDHI
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JSR SDCMD
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BCS @ERROR1
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JSR GETR3 ; R7 is also 1+4 bytes
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CMP #$01
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BNE @SDV1 ; may be SD Ver. 1
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@ -275,12 +276,14 @@ INIT: LDA #$03 ; set SPI mode 3
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LDA #>CMD55
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STA CMDHI
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JSR SDCMD
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BCS @ERROR1
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JSR GETR1
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LDA #<ACMD4140 ; enable SDHC support
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STA CMDLO
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LDA #>ACMD4140
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STA CMDHI
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JSR SDCMD
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BCS @ERROR1
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JSR GETR1
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CMP #$01
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BEQ @SDV2 ; wait for ready
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@ -293,6 +296,7 @@ INIT: LDA #$03 ; set SPI mode 3
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LDA #>CMD58
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STA CMDHI
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JSR SDCMD
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BCS @ERROR1
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JSR GETR3
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CMP #0
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BNE @ERROR1 ; error!
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@ -313,11 +317,13 @@ INIT: LDA #$03 ; set SPI mode 3
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LDA #>CMD55
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STA CMDHI
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JSR SDCMD ; ignore response
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BCS @ERROR1
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LDA #<ACMD410
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STA CMDLO
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LDA #>ACMD410
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STA CMDHI
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JSR SDCMD
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BCS @ERROR1
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JSR GETR1
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CMP #$01
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BEQ @SDV1 ; wait for ready
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@ -331,6 +337,7 @@ INIT: LDA #$03 ; set SPI mode 3
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LDA #>CMD1
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STA CMDHI
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@LOOP1: JSR SDCMD
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BCS @IOERROR
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JSR GETR1
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CMP #$01
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BEQ @LOOP1 ; wait for ready
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@ -343,6 +350,7 @@ INIT: LDA #$03 ; set SPI mode 3
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LDA #>CMD16
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STA CMDHI
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JSR SDCMD
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BCS @IOERROR
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JSR GETR1
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CMP #0
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BNE @IOERROR ; error!
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@ -350,9 +358,9 @@ INIT: LDA #$03 ; set SPI mode 3
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@END: LDA SS,X
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ORA #INITED ; initialized
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STA SS,X
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LDA CTRL,X
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ORA #ECE ; enable 7MHz
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STA CTRL,X
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;LDA CTRL,X
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;ORA #ECE ; enable 7MHz
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;STA CTRL,X
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CLC ; all ok
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LDY #NO_ERR
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BCC @END1
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@ -368,7 +376,7 @@ INIT: LDA #$03 ; set SPI mode 3
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RTS
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TEXT: .asciiz " Apple][Sd v1.2.1 (c)2018 Florian Reitz "
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TEXT: .asciiz " Apple][Sd v1.2.2 (c)2018 Florian Reitz "
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CMD0: .byt $40, $00, $00
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.byt $00, $00, $95
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90
src/Helper.s
90
src/Helper.s
@ -11,8 +11,10 @@
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;
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;*******************************
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.export WRDATA
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.export COMMAND
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.export SDCMD
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.export SDCMD0
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.export GETBLOCK
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.export CARDDET
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.export WRPROT
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@ -22,24 +24,56 @@
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.include "AppleIISd.inc"
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.segment "EXTROM"
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WRDATA: STA DATA,X
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@WAIT: BIT CTRL,X
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BPL @WAIT
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RTS
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;********************************
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; Wait for card ready
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; C set on timeout
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;********************************
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WREADY:
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PHA
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LDA #$FE
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@LOOP: PHA ; counter
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LDA #DUMMY
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JSR WRDATA
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LDA DATA,X
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CMP #$FF
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BNE @AGAIN
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PLA
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PLA
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CLC
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RTS
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@AGAIN: PLA
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CMP #$FF
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BEQ @TOUT
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SBC #0 ; dec a
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JMP @LOOP
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@TOUT: PLA
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SEC
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RTS
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;*******************************
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;
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; Send SD command
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; Call with command in CMDHI and CMDLO
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; Returns iwth carry set on timeout
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;
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;*******************************
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SDCMD: PHY
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SDCMD: JSR WREADY
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BCC SDCMD0
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RTS
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SDCMD0: PHY
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LDY #0
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@LOOP: LDA (CMDLO),Y
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STA DATA,X
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@WAIT: BIT CTRL,X ; TC is in N
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BPL @WAIT
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JSR WRDATA
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INY
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CPY #6
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BCC @LOOP
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PLY
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CLC
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RTS
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@ -50,16 +84,22 @@ SDCMD: PHY
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;
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;*******************************
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GETR1: LDA #DUMMY
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STA DATA,X
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@WAIT: BIT CTRL,X
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BPL @WAIT
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GETR1: PHY
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LDY #10
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@AGAIN: LDA #DUMMY
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JSR WRDATA
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LDA DATA,X ; get response
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BMI GETR1 ; wait for MSB=0
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PHA
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BIT #$80
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BEQ @CONT ; wait for MSB=0
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DEY
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BNE @AGAIN
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PLY
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RTS
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@CONT: PHA
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LDA #DUMMY
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STA DATA,X ; send another dummy
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JSR WRDATA ; send another dummy
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PLA ; restore R1
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PLY
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RTS
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;*******************************
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@ -74,12 +114,10 @@ GETR3: JSR GETR1 ; get R1 first
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PHA ; save R1
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PHY ; save Y
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LDY #04 ; load counter
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JMP @WAIT ; first byte is already there
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JMP @LOAD ; first byte is already there
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@LOOP: LDA #DUMMY ; send dummy
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STA DATA,X
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@WAIT: BIT CTRL,X
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BPL @WAIT
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LDA DATA,X
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JSR WRDATA
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@LOAD: LDA DATA,X
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PHA
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DEY
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BNE @LOOP ; do 4 times
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@ -94,7 +132,7 @@ GETR3: JSR GETR1 ; get R1 first
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STA R30,Y ; R30 is MSB
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PLY ; restore Y
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LDA #DUMMY
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STA DATA,X ; send another dummy
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JSR WRDATA ; send another dummy
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PLA ; restore R1
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RTS
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@ -156,19 +194,23 @@ GETBLOCK: PHX ; save X
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;
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;*******************************
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COMMAND: PHY ; save Y
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COMMAND:
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JSR WREADY
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BCC @CONT
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RTS
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@CONT: PHY ; save Y
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LDY SLOT
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STA DATA,X ; send command
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JSR WRDATA ; send command
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LDA R30,Y ; get arg from R30 on
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STA DATA,X
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JSR WRDATA
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LDA R31,Y
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STA DATA,X
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JSR WRDATA
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LDA R32,Y
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STA DATA,X
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JSR WRDATA
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LDA R33,Y
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STA DATA,X
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JSR WRDATA
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LDA #DUMMY
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STA DATA,X ; dummy crc
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JSR WRDATA ; dummy crc
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JSR GETR1
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PLY ; restore Y
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RTS
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25
src/ProDOS.s
25
src/ProDOS.s
@ -16,6 +16,7 @@
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.export READ
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.export WRITE
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.import WRDATA
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.import COMMAND
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.import SDCMD
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.import GETBLOCK
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@ -108,16 +109,16 @@ READ: JSR GETBLOCK ; calc block address
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BNE @ERROR ; check for error
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@GETTOK: LDA #DUMMY ; get data token
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STA DATA,X
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JSR WRDATA
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LDA DATA,X ; get response
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CMP #$FE
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BNE @GETTOK ; wait for $FE
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LDA CTRL,X ; enable FRX
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ORA #FRX
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ORA #FRX+ECE
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STA CTRL,X
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LDA #DUMMY
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STA DATA,X
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JSR WRDATA
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LDY #0
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@LOOP1: LDA DATA,X ; read data from card
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@ -136,7 +137,7 @@ READ: JSR GETBLOCK ; calc block address
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LDA DATA,X ; read a dummy byte
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LDA CTRL,X ; disable FRX
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AND #<~FRX
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AND #<~(FRX+ECE)
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STA CTRL,X
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CLC ; no error
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LDA #NO_ERR
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@ -184,27 +185,27 @@ WRITE: JSR WRPROT
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BNE @IOERROR ; check for error
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LDA #DUMMY
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STA DATA,X ; send dummy
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JSR WRDATA ; send dummy
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LDA #$FE
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STA DATA,X ; send data token
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JSR WRDATA ; send data token
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LDY #0
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@LOOP1: LDA (BUFFER),Y
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STA DATA,X
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JSR WRDATA
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INY
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BNE @LOOP1
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INC BUFFER+1
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@LOOP2: LDA (BUFFER),Y
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STA DATA,X
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JSR WRDATA
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INY
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BNE @LOOP2
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DEC BUFFER+1
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@CRC: LDA #DUMMY
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STA DATA,X ; send 2 dummy crc bytes
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STA DATA,X
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JSR WRDATA ; send 2 dummy crc bytes
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JSR WRDATA
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STA DATA,X ; get data response
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JSR WRDATA ; get data response
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LDA DATA,X
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AND #$1F
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CMP #$05
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@ -215,7 +216,7 @@ WRITE: JSR WRPROT
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@DONE: PHP
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PHA
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@WAIT: LDA #DUMMY
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STA DATA,X ; wait for write cycle
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JSR WRDATA ; wait for write cycle
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LDA DATA,X ; to complete
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BEQ @WAIT
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