Apple-2-HW/AppleIISd
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freitz85 2017-09-03 14:51:09 +02:00
parent 63313fd7fa
commit 7425ad32fc
1 changed files with 332 additions and 346 deletions
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50
VHDL/AppleIISd.vhd
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@ -32,21 +32,12 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use AddressDecoder.ALL;
use AddressDecoder.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AppleIISd is
Port ( data : inout STD_LOGIC_VECTOR (7 downto 0);
Port (
data : inout STD_LOGIC_VECTOR (7 downto 0);
nrw : in STD_LOGIC;
nirq : out STD_LOGIC;
nreset : in STD_LOGIC;
@ -126,12 +117,13 @@ architecture Behavioral of AppleIISd is
-- spi clock
signal clksrc: std_logic; -- clock source (phi2 or extclk)
-- TODO divcnt is not used at all??
signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter
signal shiftclk : std_logic;
component AddressDecoder
port ( A8 : in std_logic;
port (
A8 : in std_logic;
A9 : in std_logic;
A10 : in std_logic;
CLK : in std_logic;
@ -141,12 +133,14 @@ architecture Behavioral of AppleIISd is
B8 : out std_logic;
B9 : out std_logic;
B10 : out std_logic;
NOE : out std_logic);
NOE : out std_logic
);
end component;
begin
add_dec : AddressDecoder
port map (A8=>a8,
port map (
A8=>a8,
A9=>a9,
A10=>a10,
CLK=>extclk,
@ -156,14 +150,13 @@ begin
B8=>b8,
B9=>b9,
B10=>b10,
NOE=>noe);
NOE=>noe
);
led <= not (bsy or not slavesel); --'0'; --shifting2; --shiftdone; --shiftcnt(2);
led <= not (bsy or not slavesel);
ng <= ndev_sel and nio_sel and nio_stb;
inited <= inited_int and not card;
--------------------------
bsy <= start_shifting or shifting2;
process(start_shifting, shiftdone, shiftclk)
@ -204,8 +197,7 @@ begin
end if;
end process;
inproc: process(reset, shifting2,
shiftcnt, shiftclk, spidatain, int_miso)
inproc: process(reset, shifting2, shiftcnt, shiftclk, spidatain, int_miso)
begin
if (reset='1') then
spidatain <= (others => '0');
@ -218,8 +210,7 @@ begin
end if;
end process;
outproc: process(reset, shifting2, spidataout, cpol, cpha,
shiftcnt, shiftclk)
outproc: process(reset, shifting2, spidataout, cpol, cpha, shiftcnt, shiftclk)
begin
if (reset='1') then
int_mosi <= '1';
@ -276,11 +267,9 @@ begin
begin
if (reset='1') then
divcnt <= divisor;
--spiclk <= '0';
elsif (falling_edge(clksrc)) then
if (shiftclk = '1') then
divcnt <= divisor;
--spiclk <= not(spiclk);
else
divcnt <= divcnt - 1;
end if;
@ -295,7 +284,7 @@ begin
-- interface section
-- inputs
reset <= not (nreset);
selected <= not(ndev_sel); -- and cpu_phi2;
selected <= not(ndev_sel);
is_read <= selected and nphi2 and nrw;
int_din <= data;
@ -312,10 +301,7 @@ begin
begin
if (shiftdone = '1') then
tc <= '1';
elsif (falling_edge(selected) and addr="00"
--elsif (falling_edge(cpu_phi2) and selected='1' and addr="00"
--and nrw='1' -- both reads _and_ writes clear the interrupt
) then
elsif (falling_edge(selected) and addr="00") then
tc <= '0';
end if;
end process;
@ -374,8 +360,8 @@ begin
slaveinten <= '0';
inited_int <= '0';
divisor <= (others => '0');
spidataout <= (others => '1');
elsif (falling_edge(selected) and nrw = '0') then
--elsif (falling_edge(cpu_phi2) and selected='1' and nrw='0') then
case addr is
when "00" => -- write SPI data out (see other process above)
spidataout <= int_din;