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@ -32,21 +32,12 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--use AddressDecoder.ALL;
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use AddressDecoder.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity AppleIISd is
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Port ( data : inout STD_LOGIC_VECTOR (7 downto 0);
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Port (
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data : inout STD_LOGIC_VECTOR (7 downto 0);
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nrw : in STD_LOGIC;
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nirq : out STD_LOGIC;
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nreset : in STD_LOGIC;
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@ -126,12 +117,13 @@ architecture Behavioral of AppleIISd is
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-- spi clock
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signal clksrc: std_logic; -- clock source (phi2 or extclk)
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-- TODO divcnt is not used at all??
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signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter
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signal shiftclk : std_logic;
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component AddressDecoder
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port ( A8 : in std_logic;
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port (
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A8 : in std_logic;
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A9 : in std_logic;
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A10 : in std_logic;
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CLK : in std_logic;
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@ -141,12 +133,14 @@ architecture Behavioral of AppleIISd is
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B8 : out std_logic;
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B9 : out std_logic;
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B10 : out std_logic;
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NOE : out std_logic);
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NOE : out std_logic
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);
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end component;
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begin
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add_dec : AddressDecoder
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port map (A8=>a8,
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port map (
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A8=>a8,
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A9=>a9,
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A10=>a10,
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CLK=>extclk,
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@ -156,14 +150,13 @@ begin
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B8=>b8,
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B9=>b9,
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B10=>b10,
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NOE=>noe);
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NOE=>noe
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);
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led <= not (bsy or not slavesel); --'0'; --shifting2; --shiftdone; --shiftcnt(2);
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led <= not (bsy or not slavesel);
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ng <= ndev_sel and nio_sel and nio_stb;
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inited <= inited_int and not card;
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--------------------------
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bsy <= start_shifting or shifting2;
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process(start_shifting, shiftdone, shiftclk)
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@ -204,8 +197,7 @@ begin
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end if;
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end process;
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inproc: process(reset, shifting2,
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shiftcnt, shiftclk, spidatain, int_miso)
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inproc: process(reset, shifting2, shiftcnt, shiftclk, spidatain, int_miso)
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begin
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if (reset='1') then
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spidatain <= (others => '0');
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@ -218,8 +210,7 @@ begin
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end if;
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end process;
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outproc: process(reset, shifting2, spidataout, cpol, cpha,
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shiftcnt, shiftclk)
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outproc: process(reset, shifting2, spidataout, cpol, cpha, shiftcnt, shiftclk)
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begin
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if (reset='1') then
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int_mosi <= '1';
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@ -276,11 +267,9 @@ begin
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begin
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if (reset='1') then
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divcnt <= divisor;
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--spiclk <= '0';
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elsif (falling_edge(clksrc)) then
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if (shiftclk = '1') then
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divcnt <= divisor;
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--spiclk <= not(spiclk);
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else
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divcnt <= divcnt - 1;
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end if;
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@ -295,7 +284,7 @@ begin
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-- interface section
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-- inputs
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reset <= not (nreset);
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selected <= not(ndev_sel); -- and cpu_phi2;
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selected <= not(ndev_sel);
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is_read <= selected and nphi2 and nrw;
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int_din <= data;
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@ -312,10 +301,7 @@ begin
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begin
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if (shiftdone = '1') then
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tc <= '1';
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elsif (falling_edge(selected) and addr="00"
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--elsif (falling_edge(cpu_phi2) and selected='1' and addr="00"
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--and nrw='1' -- both reads _and_ writes clear the interrupt
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) then
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elsif (falling_edge(selected) and addr="00") then
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tc <= '0';
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end if;
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end process;
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@ -374,8 +360,8 @@ begin
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slaveinten <= '0';
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inited_int <= '0';
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divisor <= (others => '0');
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spidataout <= (others => '1');
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elsif (falling_edge(selected) and nrw = '0') then
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--elsif (falling_edge(cpu_phi2) and selected='1' and nrw='0') then
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case addr is
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when "00" => -- write SPI data out (see other process above)
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spidataout <= int_din;
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