diff --git a/VHDL/AddressDecoder.sch b/VHDL/AddressDecoder.sch
index feb12bd..6bef732 100644
--- a/VHDL/AddressDecoder.sch
+++ b/VHDL/AddressDecoder.sch
@@ -9,49 +9,38 @@
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-
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diff --git a/VHDL/AddressDecoder.sym b/VHDL/AddressDecoder.sym
index 655347d..7a34ba0 100644
--- a/VHDL/AddressDecoder.sym
+++ b/VHDL/AddressDecoder.sym
@@ -1,42 +1,48 @@
BLOCK
- 2017-9-3T12:42:25
+ 2017-10-8T19:38:25
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diff --git a/VHDL/AppleIISd.ipf b/VHDL/AppleIISd.ipf
index 5fe0a05..5834bda 100644
Binary files a/VHDL/AppleIISd.ipf and b/VHDL/AppleIISd.ipf differ
diff --git a/VHDL/AppleIISd.sym b/VHDL/AppleIISd.sym
new file mode 100644
index 0000000..18eecf0
--- /dev/null
+++ b/VHDL/AppleIISd.sym
@@ -0,0 +1,57 @@
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+ BLOCK
+ 2017-10-8T19:42:44
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diff --git a/VHDL/AppleIISd.ucf b/VHDL/AppleIISd.ucf
index 733dfa6..c3dd45b 100644
--- a/VHDL/AppleIISd.ucf
+++ b/VHDL/AppleIISd.ucf
@@ -1,38 +1,38 @@
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
-NET "a10" LOC = "P38" ;
-NET "a8" LOC = "P36" ;
-NET "a9" LOC = "P37" ;
-NET "addr<0>" LOC = "P19" ;
-NET "addr<1>" LOC = "P18" ;
-NET "b10" LOC = "P22" ;
-NET "b8" LOC = "P26" ;
-NET "b9" LOC = "P27" ;
-NET "card" LOC = "P33" ;
-NET "data<0>" LOC = "P3" ;
-NET "data<1>" LOC = "P4" ;
-NET "data<2>" LOC = "P5" ;
-NET "data<3>" LOC = "P6" ;
-NET "data<4>" LOC = "P7" ;
-NET "data<5>" LOC = "P9" ;
-NET "data<6>" LOC = "P11" ;
-NET "data<7>" LOC = "P13" ;
-NET "clk_7m" LOC = "P43" ;
-NET "led" LOC = "P29" ;
-NET "ndev_sel" LOC = "P24" ;
-NET "ng" LOC = "P12" ;
-NET "nio_sel" LOC = "P14" ;
-NET "nio_stb" LOC = "P42" ;
-NET "noe" LOC = "P25" ;
-NET "clk_phi0" LOC = "P8" ;
-NET "nreset" LOC = "P20" ;
-NET "nrw" LOC = "P1" ;
-NET "spi_miso" LOC = "P40" ;
-NET "spi_mosi" LOC = "P35" ;
-NET "spi_Nsel" LOC = "P28" ;
-NET "spi_sclk" LOC = "P34" ;
-NET "wp" LOC = "P39" ;
+NET "A10" LOC = "P38" ;
+NET "A8" LOC = "P36" ;
+NET "A9" LOC = "P37" ;
+NET "A0" LOC = "P19" ;
+NET "A1" LOC = "P18" ;
+NET "B10" LOC = "P22" ;
+NET "B8" LOC = "P26" ;
+NET "B9" LOC = "P27" ;
+NET "CARD" LOC = "P33" ;
+NET "DATA<0>" LOC = "P3" ;
+NET "DATA<1>" LOC = "P4" ;
+NET "DATA<2>" LOC = "P5" ;
+NET "DATA<3>" LOC = "P6" ;
+NET "DATA<4>" LOC = "P7" ;
+NET "DATA<5>" LOC = "P9" ;
+NET "DATA<6>" LOC = "P11" ;
+NET "DATA<7>" LOC = "P13" ;
+NET "CLK" LOC = "P43" ;
+NET "LED" LOC = "P29" ;
+NET "NDEV_SEL" LOC = "P24" ;
+NET "NG" LOC = "P12" ;
+NET "NIO_SEL" LOC = "P14" ;
+NET "NIO_STB" LOC = "P42" ;
+NET "NOE" LOC = "P25" ;
+NET "PHI0" LOC = "P8" ;
+NET "NRESET" LOC = "P20" ;
+NET "RNW" LOC = "P1" ;
+NET "MISO" LOC = "P40" ;
+NET "MOSI" LOC = "P35" ;
+NET "NSEL" LOC = "P28" ;
+NET "SCLK" LOC = "P34" ;
+NET "WP" LOC = "P39" ;
#PACE: Start of PACE Area Constraints
diff --git a/VHDL/AppleIISd.vhd b/VHDL/AppleIISd.vhd
index 8f405c7..a1cefdc 100644
--- a/VHDL/AppleIISd.vhd
+++ b/VHDL/AppleIISd.vhd
@@ -36,31 +36,21 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity AppleIISd is
Port (
- data : inout STD_LOGIC_VECTOR (7 downto 0);
- nrw : in STD_LOGIC;
- nreset : in STD_LOGIC;
+ data_in : in STD_LOGIC_VECTOR (7 downto 0);
+ data_out : out STD_LOGIC_VECTOR (7 downto 0);
+ is_read : in STD_LOGIC;
+ reset : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (1 downto 0);
- clk_phi0 : in STD_LOGIC;
- ndev_sel : in STD_LOGIC;
- clk_7m : in STD_LOGIC;
- spi_miso: in std_logic;
- spi_mosi : out STD_LOGIC;
- spi_sclk : out STD_LOGIC;
- spi_Nsel : out STD_LOGIC;
+ phi0 : in STD_LOGIC;
+ selected : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ miso: in std_logic;
+ mosi : out STD_LOGIC;
+ sclk : out STD_LOGIC;
+ nsel : out STD_LOGIC;
wp : in STD_LOGIC;
card : in STD_LOGIC;
- led : out STD_LOGIC;
-
- a8 : in std_logic;
- a9 : in std_logic;
- a10 : in std_logic;
- nio_sel : in std_logic;
- nio_stb : in std_logic;
- b8 : out std_logic;
- b9 : out std_logic;
- b10 : out std_logic;
- noe : out std_logic;
- ng : out std_logic
+ led : out STD_LOGIC
);
constant DIV_WIDTH : integer := 3;
@@ -69,36 +59,21 @@ end AppleIISd;
architecture Behavioral of AppleIISd is
- -- interface signals
- signal selected: std_logic;
- signal reset: std_logic;
- signal is_read: std_logic;
- signal int_din: std_logic_vector (7 downto 0);
- signal int_dout: std_logic_vector (7 downto 0);
-
- signal int_mosi: std_logic;
- signal int_miso: std_logic;
- signal int_sclk: std_logic;
-
--------------------------
-- internal state
signal spidatain: std_logic_vector (7 downto 0);
signal spidataout: std_logic_vector (7 downto 0);
signal inited: std_logic; -- card initialized
- signal inited_set: std_logic;
-- spi register flags
signal tc: std_logic; -- transmission complete; cleared on spi data read
signal bsy: std_logic; -- SPI busy
signal frx: std_logic; -- fast receive mode
- signal tmo: std_logic; -- tri-state mosi
signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock
- signal cpol: std_logic; -- shift clock polarity; 0=rising edge, 1=falling edge
- signal cpha: std_logic; -- shift clock phase; 0=leading edge, 1=rising edge
signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0);
signal slavesel: std_logic; -- slave select output (0=selected)
-
+ signal int_miso: std_logic;
--------------------------
-- helper signals
@@ -111,56 +86,15 @@ architecture Behavioral of AppleIISd is
-- spi clock
signal clksrc: std_logic; -- clock source (phi2 or clk_7m)
-- TODO divcnt is not used at all??
- signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter
+ --signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter
signal shiftclk : std_logic;
-
- component AddressDecoder
- port (
- A8 : in std_logic;
- A9 : in std_logic;
- A10 : in std_logic;
- CLK : in std_logic;
- NDEV_SEL : in std_logic;
- NIO_SEL : in std_logic;
- NIO_STB : in std_logic;
- RNW : in std_logic;
- B8 : out std_logic;
- B9 : out std_logic;
- B10 : out std_logic;
- NOE : out std_logic
- );
- end component;
-begin
- add_dec : AddressDecoder
- port map (
- A8 => a8,
- A9 => a9,
- A10 => a10,
- CLK => clk_7m,
- NDEV_SEL => ndev_sel,
- NIO_SEL => nio_sel,
- NIO_STB => nio_stb,
- RNW => nrw,
- B8 => b8,
- B9 => b9,
- B10 => b10,
- NOE => noe);
-
- led <= not (inited_set);
+begin
+ --led <= not (inited);
+ led <= not bsy;
--led <= not (bsy or not slavesel);
- ng <= ndev_sel and nio_sel and nio_stb;
bsy <= start_shifting or shifting2;
- process(clk_7m, reset, card, inited_set)
- begin
- if(reset = '1' or card = '1') then
- inited <= '0';
- elsif rising_edge(inited_set) then
- inited <= '1';
- end if;
- end process;
-
process(start_shifting, shiftdone, shiftclk)
begin
if (rising_edge(shiftclk)) then
@@ -199,7 +133,7 @@ begin
end if;
end process;
- inproc: process(reset, shifting2, shiftcnt, shiftclk, spidatain, int_miso)
+ inproc: process(reset, shifting2, shiftcnt, shiftclk, spidatain, miso)
begin
if (reset='1') then
spidatain <= (others => '0');
@@ -212,31 +146,31 @@ begin
end if;
end process;
- outproc: process(reset, shifting2, spidataout, cpol, cpha, shiftcnt, shiftclk)
+ outproc: process(reset, shifting2, spidataout, shiftcnt, shiftclk)
begin
if (reset='1') then
- int_mosi <= '1';
- int_sclk <= cpol;
+ mosi <= '1';
+ sclk <= '0';
else
-- clock is sync'd
if (rising_edge(shiftclk)) then
if (shifting2='0' or shiftdone = '1') then
- int_mosi <= '1';
- int_sclk <= cpol;
+ mosi <= '1';
+ sclk <= '0';
else
-- output data directly from output register
case shiftcnt(3 downto 1) is
- when "000" => int_mosi <= spidataout(7);
- when "001" => int_mosi <= spidataout(6);
- when "010" => int_mosi <= spidataout(5);
- when "011" => int_mosi <= spidataout(4);
- when "100" => int_mosi <= spidataout(3);
- when "101" => int_mosi <= spidataout(2);
- when "110" => int_mosi <= spidataout(1);
- when "111" => int_mosi <= spidataout(0);
- when others => int_mosi <= '1';
+ when "000" => mosi <= spidataout(7);
+ when "001" => mosi <= spidataout(6);
+ when "010" => mosi <= spidataout(5);
+ when "011" => mosi <= spidataout(4);
+ when "100" => mosi <= spidataout(3);
+ when "101" => mosi <= spidataout(2);
+ when "110" => mosi <= spidataout(1);
+ when "111" => mosi <= spidataout(0);
+ when others => mosi <= '1';
end case;
- int_sclk <= cpol xor cpha xor shiftcnt(0);
+ sclk <= '0' xor '0' xor shiftcnt(0);
end if;
end if;
end if;
@@ -244,13 +178,13 @@ begin
-- shift operation enable
- shiften: process(reset, selected, nrw, addr, frx, shiftdone)
+ shiften: process(reset, selected, is_read, addr, frx, shiftdone)
begin
-- start shifting
if (reset='1' or shiftdone='1') then
start_shifting <= '0';
- elsif (falling_edge(selected) and addr="00" and (frx='1' or nrw='0')) then
- -- access to register 00, either write (nrw=0) or fast receive bit set (frx)
+ elsif (falling_edge(selected) and addr="00" and (frx='1' or is_read='0')) then
+ -- access to register 00, either write (is_read=0) or fast receive bit set (frx)
-- then both types of access (write but also read)
start_shifting <= '1';
end if;
@@ -259,49 +193,33 @@ begin
--------------------------
-- spiclk - spi clock generation
-- spiclk is still 2 times the freq. than sclk
- clksrc <= clk_phi0 when (ece = '0') else clk_7m;
+ clksrc <= phi0 when (ece = '0') else clk;
-- is a pulse signal to allow for divisor==0
--shiftclk <= clksrc when divcnt = "000000" else '0';
shiftclk <= clksrc when bsy = '1' else '0';
- clkgen: process(reset, divisor, clksrc)
- begin
- if (reset='1') then
- divcnt <= divisor;
- elsif (falling_edge(clksrc)) then
- if (shiftclk = '1') then
- divcnt <= divisor;
- else
- divcnt <= divcnt - 1;
- end if;
- end if;
- end process;
+-- clkgen: process(reset, divisor, clksrc)
+-- begin
+-- if (reset='1') then
+-- divcnt <= divisor;
+-- elsif (falling_edge(clksrc)) then
+-- if (shiftclk = '1') then
+-- divcnt <= divisor;
+-- else
+-- divcnt <= divcnt - 1;
+-- end if;
+-- end if;
+-- end process;
--------------------------
-- interface section
-- inputs
- reset <= not (nreset);
- selected <= not(ndev_sel);
- int_din <= data;
- int_miso <= (spi_miso and not slavesel);
-
- process(selected, clk_7m)
- begin
- if(selected = '0') then
- is_read <= '0';
- elsif(rising_edge(clk_7m) and selected = '1' and clk_phi0 = '1' and nrw = '1') then
- is_read <= '1';
- end if;
- end process;
-
+ int_miso <= (miso and not slavesel);
+
-- outputs
- data <= int_dout when (is_read='1') else (others => 'Z'); -- data bus tristate
- spi_sclk <= int_sclk;
- spi_mosi <= int_mosi when tmo='0' else 'Z'; -- mosi tri-state
- spi_Nsel <= slavesel;
+ nsel <= slavesel;
-
tc_proc: process (selected, shiftdone)
begin
if (shiftdone = '1') then
@@ -314,72 +232,61 @@ begin
--------------------------
-- cpu register section
-- cpu read
- cpu_read: process (is_read, addr,
- spidatain, tc, bsy, frx, tmo, ece, cpol, cpha, divisor,
- slavesel, wp, card, inited)
+ cpu_read: process(addr, spidatain, tc, bsy, frx,
+ ece, divisor, slavesel, wp, card, inited)
begin
- if (is_read = '1') then
- case addr is
- when "00" => -- read SPI data in
- int_dout <= spidatain;
- when "01" => -- read status register
- int_dout(0) <= cpha;
- int_dout(1) <= cpol;
- int_dout(2) <= ece;
- int_dout(3) <= tmo;
- int_dout(4) <= frx;
- int_dout(5) <= bsy;
- int_dout(6) <= '0';
- int_dout(7) <= tc;
- when "10" => -- read sclk divisor
- int_dout(DIV_WIDTH-1 downto 0) <= divisor;
- int_dout(7 downto 3) <= (others => '0');
- when "11" => -- read slave select / slave interrupt state
- int_dout(0) <= slavesel;
- int_dout(4 downto 1) <= (others => '0');
- int_dout(5) <= wp;
- int_dout(6) <= card;
- int_dout(7) <= inited;
- when others =>
- int_dout <= (others => '0');
- end case;
- else
- int_dout <= (others => '0');
- end if;
+ case addr is
+ when "00" => -- read SPI data in
+ data_out <= spidatain;
+ when "01" => -- read status register
+ data_out(0) <= '0';
+ data_out(1) <= '0';
+ data_out(2) <= ece;
+ data_out(3) <= '0';
+ data_out(4) <= frx;
+ data_out(5) <= bsy;
+ data_out(6) <= '0';
+ data_out(7) <= tc;
+ when "10" => -- read sclk divisor
+ data_out(DIV_WIDTH-1 downto 0) <= divisor;
+ data_out(7 downto 3) <= (others => '0');
+ when "11" => -- read slave select / slave interrupt state
+ data_out(0) <= slavesel;
+ data_out(4 downto 1) <= (others => '0');
+ data_out(5) <= wp;
+ data_out(6) <= card;
+ data_out(7) <= inited;
+ when others =>
+ data_out <= (others => '0');
+ end case;
end process;
-- cpu write
- cpu_write: process(reset, selected, nrw, addr, int_din, card, inited)
+ cpu_write: process(reset, selected, is_read, addr, data_in, card, inited)
begin
if (reset = '1') then
- cpha <= '0';
- cpol <= '0';
ece <= '0';
- tmo <= '0';
frx <= '0';
slavesel <= '1';
divisor <= (others => '0');
spidataout <= (others => '1');
- inited_set <= '0';
+ inited <= '0';
elsif (card = '1') then
- inited_set <= '0';
- elsif (falling_edge(selected) and nrw = '0') then
+ inited <= '0';
+ elsif (falling_edge(selected) and is_read = '0') then
case addr is
when "00" => -- write SPI data out (see other process above)
- spidataout <= int_din;
+ spidataout <= data_in;
when "01" => -- write status register
- cpha <= int_din(0);
- cpol <= int_din(1);
- ece <= int_din(2);
- tmo <= int_din(3);
- frx <= int_din(4);
+ ece <= data_in(2);
+ frx <= data_in(4);
-- no bit 5 - 7
when "10" => -- write divisor
- divisor <= int_din(DIV_WIDTH-1 downto 0);
+ divisor <= data_in(DIV_WIDTH-1 downto 0);
when "11" => -- write slave select / slave interrupt enable
- slavesel <= int_din(0);
+ slavesel <= data_in(0);
-- no bit 1 - 6
- inited_set <= int_din(7);
+ inited <= data_in(7);
when others =>
end case;
end if;
diff --git a/VHDL/AppleIISd.xise b/VHDL/AppleIISd.xise
index d171fcd..32d3070 100644
--- a/VHDL/AppleIISd.xise
+++ b/VHDL/AppleIISd.xise
@@ -17,15 +17,19 @@
-
+
-
+
+
+
+
+
@@ -42,7 +46,7 @@
-
+
@@ -74,10 +78,10 @@
-
-
-
-
+
+
+
+
@@ -86,10 +90,13 @@
+
+
+
-
+
@@ -112,14 +119,14 @@
-
+
-
+
-
+
@@ -161,14 +168,15 @@
-
-
-
+
+
+
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diff --git a/VHDL/in_buf.jhd b/VHDL/in_buf.jhd
new file mode 100644
index 0000000..c7e41e4
--- /dev/null
+++ b/VHDL/in_buf.jhd
@@ -0,0 +1 @@
+MODULE in_buf
diff --git a/VHDL/in_buf.sch b/VHDL/in_buf.sch
new file mode 100644
index 0000000..b942ea5
--- /dev/null
+++ b/VHDL/in_buf.sch
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\ No newline at end of file
diff --git a/VHDL/io_buffers.sch b/VHDL/io_buffers.sch
new file mode 100644
index 0000000..4afd2dd
--- /dev/null
+++ b/VHDL/io_buffers.sch
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\ No newline at end of file
diff --git a/VHDL/io_buffers.tim b/VHDL/io_buffers.tim
new file mode 100644
index 0000000..e69de29
diff --git a/VHDL/sch2HdlBatchFile b/VHDL/sch2HdlBatchFile
index a1d9453..6e0be78 100644
--- a/VHDL/sch2HdlBatchFile
+++ b/VHDL/sch2HdlBatchFile
@@ -1 +1 @@
-sch2hdl,-intstyle,ise,-family,xc9500xl,-verilog,U:/AppleIISd/VHDL/AddressDecoder.vf,-w,U:/AppleIISd/VHDL/AddressDecoder.sch
+sch2hdl,-intstyle,ise,-family,xc9500xl,-verilog,U:/AppleIISd/VHDL/io_buffers.vf,-w,U:/AppleIISd/VHDL/io_buffers.sch