NWE signal added, not tested

VHDL/AddressDecoder.vhd

@@ -31,18 +31,19 @@ use IEEE.STD_LOGIC_1164.ALL;
 
 entity AddressDecoder is
     Port ( A : in  std_logic_vector (11 downto 8);
-           B : out  std_logic_vector (10 downto 8); -- to EPROM
+           B : out  std_logic_vector (10 downto 8); -- to EEPROM
            CLK : in std_logic;
            PHI0 : in std_logic;
            RNW : in  std_logic;
-           NDEV_SEL : in  std_logic;    -- $C0n0 - $C0nF
-           NIO_SEL : in  std_logic;     -- $Cs00 - $CsFF
-           NIO_STB : in  std_logic;     -- $C800 - $CFFF
+           NDEV_SEL : in  std_logic;    -- $C0n0 - $C0nF, CPLD registers
+           NIO_SEL : in  std_logic;     -- $Cs00 - $CsFF, EEPROM bank 0
+           NIO_STB : in  std_logic;     -- $C800 - $CFFF, EEPROM banks 1 to 7
            NRESET : in std_logic;
            DATA_EN : out  std_logic;    -- to CPLD
            NG : out  std_logic;         -- to bus transceiver
-           NOE : out  std_logic;
-           LED : out  std_logic);       -- to EPROM
+           NOE : out  std_logic;        -- to EEPROM
+           NWE : out std_logic;         -- to EEPROM
+           LED : out  std_logic);       
 end AddressDecoder;
 
 architecture Behavioral of AddressDecoder is
@@ -81,6 +82,9 @@ begin
     NOE  <= not RNW 
          or not NDEV_SEL
          or (not NIO_STB and ncs);
+    NWE  <= RNW
+         or not NDEV_SEL
+         or (not NIO_STB and ncs);
     
     cfxx <= a_int(8) and a_int(9) and a_int(10) and not nio_stb_int;
     

VHDL/AddressDecoder_Test.vhd

@@ -53,6 +53,7 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
          DATA_EN : OUT  std_logic;
          NG : OUT  std_logic;
          NOE : OUT  std_logic;
+         NWE : OUT  std_logic;
          LED : OUT  std_logic
         );
     END COMPONENT;
@@ -73,6 +74,7 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
    signal DATA_EN : std_logic;
    signal NG : std_logic;
    signal NOE : std_logic;
+   signal NWE : std_logic;
    signal LED : std_logic;
    
    -- Clock period definitions
@@ -94,6 +96,7 @@ BEGIN
           DATA_EN => DATA_EN,
           NG => NG,
           NOE => NOE,
+          NWE => NWE,
           LED => LED
         );
  
@@ -152,16 +155,34 @@ BEGIN
       wait until falling_edge(PHI0);
       NIO_STB <= '1';
       wait until rising_edge(PHI0);
+
+      -- C8xx write access, selected
+      RNW <= '0'
+      wait until rising_edge(PHI0);
+      NIO_STB <= '0';
+      wait until falling_edge(PHI0);
+      NIO_STB <= '1';
+      wait until rising_edge(PHI0);
       
       -- C9xx access, selected
+      RNW <= '1';
       A <= "1001";  -- must become "010"      
       wait until rising_edge(PHI0);
       NIO_STB <= '0';
       wait until falling_edge(PHI0);
       NIO_STB <= '1';
       wait until rising_edge(PHI0);
+
+      -- C9xx access write, selected
+      RNW <= '0';     
+      wait until rising_edge(PHI0);
+      NIO_STB <= '0';
+      wait until falling_edge(PHI0);
+      NIO_STB <= '1';
+      wait until rising_edge(PHI0);
       
       -- CPLD access
+      RNW <= '1';
       A <= "0101";  -- must become "000"      
       wait until rising_edge(PHI0);
       NDEV_SEL <= '0';

VHDL/AppleIISd.ucf

@@ -28,6 +28,7 @@ NET "NG"  LOC = "P12"  ;
 NET "NIO_SEL"  LOC = "P14"  ;
 NET "NIO_STB"  LOC = "P42"  ;
 NET "NOE"  LOC = "P25"  ;
+NET "NWE"  LOC = "P5"  ;
 NET "PHI0"  LOC = "P8"  ;
 NET "NRESET"  LOC = "P20"  ;
 NET "RNW"  LOC = "P1"  ;

VHDL/AppleIISd.vhd

@@ -43,6 +43,7 @@ Port (
     NIO_SEL : in std_logic;
     NIO_STB : in std_logic;
     NOE : out std_logic;
+    NWE : out std_logic;
     PHI0 : in std_logic;
     NRESET : in std_logic;
     RNW : in std_logic;
@@ -90,7 +91,7 @@ Port (
     );
 end component;
 
-component AddressDecoder
+component AddressDecoder
 Port ( 
         A : in  std_logic_vector (11 downto 8);
         B : out  std_logic_vector (10 downto 8);
@@ -104,9 +105,11 @@ Port (
         DATA_EN : out  std_logic;
         NG : out  std_logic;
         NOE : out  std_logic;
+        NWE : out std_logic;
         LED : out std_logic
-      );
-end component;
+      );
+end component;
+
 
 begin
     spi: SpiController port map(
@@ -139,6 +142,7 @@ begin
         NRESET => NRESET,
         DATA_EN => data_en,
         NOE => NOE,
+        NWE => NWE,
         NG => NG
         --LED => LED
     );