NWE signal added, not tested

This commit is contained in:
Florian Reitz 2019-02-10 12:47:46 +01:00
parent 6ed5304e10
commit b50b1037fd
4 changed files with 39 additions and 9 deletions

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@ -31,18 +31,19 @@ use IEEE.STD_LOGIC_1164.ALL;
entity AddressDecoder is entity AddressDecoder is
Port ( A : in std_logic_vector (11 downto 8); Port ( A : in std_logic_vector (11 downto 8);
B : out std_logic_vector (10 downto 8); -- to EPROM B : out std_logic_vector (10 downto 8); -- to EEPROM
CLK : in std_logic; CLK : in std_logic;
PHI0 : in std_logic; PHI0 : in std_logic;
RNW : in std_logic; RNW : in std_logic;
NDEV_SEL : in std_logic; -- $C0n0 - $C0nF NDEV_SEL : in std_logic; -- $C0n0 - $C0nF, CPLD registers
NIO_SEL : in std_logic; -- $Cs00 - $CsFF NIO_SEL : in std_logic; -- $Cs00 - $CsFF, EEPROM bank 0
NIO_STB : in std_logic; -- $C800 - $CFFF NIO_STB : in std_logic; -- $C800 - $CFFF, EEPROM banks 1 to 7
NRESET : in std_logic; NRESET : in std_logic;
DATA_EN : out std_logic; -- to CPLD DATA_EN : out std_logic; -- to CPLD
NG : out std_logic; -- to bus transceiver NG : out std_logic; -- to bus transceiver
NOE : out std_logic; NOE : out std_logic; -- to EEPROM
LED : out std_logic); -- to EPROM NWE : out std_logic; -- to EEPROM
LED : out std_logic);
end AddressDecoder; end AddressDecoder;
architecture Behavioral of AddressDecoder is architecture Behavioral of AddressDecoder is
@ -81,6 +82,9 @@ begin
NOE <= not RNW NOE <= not RNW
or not NDEV_SEL or not NDEV_SEL
or (not NIO_STB and ncs); or (not NIO_STB and ncs);
NWE <= RNW
or not NDEV_SEL
or (not NIO_STB and ncs);
cfxx <= a_int(8) and a_int(9) and a_int(10) and not nio_stb_int; cfxx <= a_int(8) and a_int(9) and a_int(10) and not nio_stb_int;

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@ -53,6 +53,7 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
DATA_EN : OUT std_logic; DATA_EN : OUT std_logic;
NG : OUT std_logic; NG : OUT std_logic;
NOE : OUT std_logic; NOE : OUT std_logic;
NWE : OUT std_logic;
LED : OUT std_logic LED : OUT std_logic
); );
END COMPONENT; END COMPONENT;
@ -73,6 +74,7 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
signal DATA_EN : std_logic; signal DATA_EN : std_logic;
signal NG : std_logic; signal NG : std_logic;
signal NOE : std_logic; signal NOE : std_logic;
signal NWE : std_logic;
signal LED : std_logic; signal LED : std_logic;
-- Clock period definitions -- Clock period definitions
@ -94,6 +96,7 @@ BEGIN
DATA_EN => DATA_EN, DATA_EN => DATA_EN,
NG => NG, NG => NG,
NOE => NOE, NOE => NOE,
NWE => NWE,
LED => LED LED => LED
); );
@ -153,7 +156,16 @@ BEGIN
NIO_STB <= '1'; NIO_STB <= '1';
wait until rising_edge(PHI0); wait until rising_edge(PHI0);
-- C8xx write access, selected
RNW <= '0'
wait until rising_edge(PHI0);
NIO_STB <= '0';
wait until falling_edge(PHI0);
NIO_STB <= '1';
wait until rising_edge(PHI0);
-- C9xx access, selected -- C9xx access, selected
RNW <= '1';
A <= "1001"; -- must become "010" A <= "1001"; -- must become "010"
wait until rising_edge(PHI0); wait until rising_edge(PHI0);
NIO_STB <= '0'; NIO_STB <= '0';
@ -161,7 +173,16 @@ BEGIN
NIO_STB <= '1'; NIO_STB <= '1';
wait until rising_edge(PHI0); wait until rising_edge(PHI0);
-- C9xx access write, selected
RNW <= '0';
wait until rising_edge(PHI0);
NIO_STB <= '0';
wait until falling_edge(PHI0);
NIO_STB <= '1';
wait until rising_edge(PHI0);
-- CPLD access -- CPLD access
RNW <= '1';
A <= "0101"; -- must become "000" A <= "0101"; -- must become "000"
wait until rising_edge(PHI0); wait until rising_edge(PHI0);
NDEV_SEL <= '0'; NDEV_SEL <= '0';

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@ -28,6 +28,7 @@ NET "NG" LOC = "P12" ;
NET "NIO_SEL" LOC = "P14" ; NET "NIO_SEL" LOC = "P14" ;
NET "NIO_STB" LOC = "P42" ; NET "NIO_STB" LOC = "P42" ;
NET "NOE" LOC = "P25" ; NET "NOE" LOC = "P25" ;
NET "NWE" LOC = "P5" ;
NET "PHI0" LOC = "P8" ; NET "PHI0" LOC = "P8" ;
NET "NRESET" LOC = "P20" ; NET "NRESET" LOC = "P20" ;
NET "RNW" LOC = "P1" ; NET "RNW" LOC = "P1" ;

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@ -43,6 +43,7 @@ Port (
NIO_SEL : in std_logic; NIO_SEL : in std_logic;
NIO_STB : in std_logic; NIO_STB : in std_logic;
NOE : out std_logic; NOE : out std_logic;
NWE : out std_logic;
PHI0 : in std_logic; PHI0 : in std_logic;
NRESET : in std_logic; NRESET : in std_logic;
RNW : in std_logic; RNW : in std_logic;
@ -104,10 +105,12 @@ Port (
DATA_EN : out std_logic; DATA_EN : out std_logic;
NG : out std_logic; NG : out std_logic;
NOE : out std_logic; NOE : out std_logic;
NWE : out std_logic;
LED : out std_logic LED : out std_logic
); );
end component; end component;
begin begin
spi: SpiController port map( spi: SpiController port map(
data_in => data_in, data_in => data_in,
@ -139,6 +142,7 @@ begin
NRESET => NRESET, NRESET => NRESET,
DATA_EN => data_en, DATA_EN => data_en,
NOE => NOE, NOE => NOE,
NWE => NWE,
NG => NG NG => NG
--LED => LED --LED => LED
); );