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freitz85 2017-10-09 22:35:47 +02:00
parent c41ff87f8f
commit b888590d11
6 changed files with 422 additions and 18 deletions
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79
VHDL/AddressDecoder_Test.vhd Normal file
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@ -0,0 +1,79 @@
-- Vhdl test bench created from schematic U:\AppleIISd\VHDL\AddressDecoder.sch - Mon Oct 09 20:12:16 2017
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY AddressDecoder_AddressDecoder_sch_tb IS
END AddressDecoder_AddressDecoder_sch_tb;
ARCHITECTURE behavioral OF AddressDecoder_AddressDecoder_sch_tb IS
COMPONENT AddressDecoder
PORT( A10 : IN STD_LOGIC;
A9 : IN STD_LOGIC;
A8 : IN STD_LOGIC;
B10 : OUT STD_LOGIC;
B9 : OUT STD_LOGIC;
B8 : OUT STD_LOGIC;
NIO_SEL : IN STD_LOGIC;
NDEV_SEL : IN STD_LOGIC;
NOE : OUT STD_LOGIC;
RNW : IN STD_LOGIC;
NG : OUT STD_LOGIC;
DATA_EN : OUT STD_LOGIC;
NIO_STB : IN STD_LOGIC);
END COMPONENT;
SIGNAL A10 : STD_LOGIC := '0';
SIGNAL A9 : STD_LOGIC := '0';
SIGNAL A8 : STD_LOGIC := '0';
SIGNAL B10 : STD_LOGIC;
SIGNAL B9 : STD_LOGIC;
SIGNAL B8 : STD_LOGIC;
SIGNAL NIO_SEL : STD_LOGIC := '1';
SIGNAL NDEV_SEL : STD_LOGIC := '1';
SIGNAL NOE : STD_LOGIC;
SIGNAL RNW : STD_LOGIC := '1';
SIGNAL NG : STD_LOGIC;
SIGNAL DATA_EN : STD_LOGIC;
SIGNAL NIO_STB : STD_LOGIC := '1';
BEGIN
UUT: AddressDecoder PORT MAP(
A10 => A10,
A9 => A9,
A8 => A8,
B10 => B10,
B9 => B9,
B8 => B8,
NIO_SEL => NIO_SEL,
NDEV_SEL => NDEV_SEL,
NOE => NOE,
RNW => RNW,
NG => NG,
DATA_EN => DATA_EN,
NIO_STB => NIO_STB
);
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
WAIT; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;

43
VHDL/AppleIISd.xise
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@ -20,14 +20,22 @@
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="AddressDecoder.sch" xil_pn:type="FILE_SCHEMATIC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="io_buffers.sch" xil_pn:type="FILE_SCHEMATIC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<file xil_pn:name="AddressDecoder_Test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="AppleIISd_Test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="IO.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
</files>
@ -62,10 +70,11 @@
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
@ -79,14 +88,14 @@
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|io_buffers" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="io_buffers.sch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/io_buffers" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|IO|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="IO.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/IO" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
@ -119,15 +128,15 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="io_buffers" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="IO" xil_pn:valueState="default"/>
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="PC44" xil_pn:valueState="default"/>
<property xil_pn:name="Pipelining" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="io_buffers_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="IO_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
@ -135,7 +144,7 @@
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="IO" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
@ -143,18 +152,18 @@
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/SR_Latch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.SR_Latch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/io_buffers/XLXI_17" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AppleIISd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Signature /User Code" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.SR_Latch" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AppleIISd" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
@ -189,7 +198,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AppleIISd|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>

137
VHDL/AppleIISd_Test.vhd Normal file
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@ -0,0 +1,137 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:21:20 10/09/2017
-- Design Name:
-- Module Name: U:/AppleIISd/VHDL/AppleIISd_Test.vhd
-- Project Name: AppleIISd
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: AppleIISd
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY AppleIISd_Test IS
END AppleIISd_Test;
ARCHITECTURE behavior OF AppleIISd_Test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT AppleIISd
PORT(
data_in : IN std_logic_vector(7 downto 0);
data_out : OUT std_logic_vector(7 downto 0);
is_read : IN std_logic;
reset : IN std_logic;
addr : IN std_logic_vector(1 downto 0);
phi0 : IN std_logic;
selected : IN std_logic;
clk : IN std_logic;
miso : IN std_logic;
mosi : OUT std_logic;
sclk : OUT std_logic;
nsel : OUT std_logic;
wp : IN std_logic;
card : IN std_logic;
led : OUT std_logic
);
END COMPONENT;
--Inputs
signal data_in : std_logic_vector(7 downto 0) := (others => '0');
signal is_read : std_logic := '0';
signal reset : std_logic := '0';
signal addr : std_logic_vector(1 downto 0) := (others => '0');
signal phi0 : std_logic := '1';
signal selected : std_logic := '0';
signal clk : std_logic := '0';
signal miso : std_logic := '0';
signal wp : std_logic := '0';
signal card : std_logic := '0';
--Outputs
signal data_out : std_logic_vector(7 downto 0);
signal mosi : std_logic;
signal sclk : std_logic;
signal nsel : std_logic;
signal led : std_logic;
-- Clock period definitions
constant clk_period : time := 142 ns; -- 7MHz
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: AppleIISd PORT MAP (
data_in => data_in,
data_out => data_out,
is_read => is_read,
reset => reset,
addr => addr,
phi0 => phi0,
selected => selected,
clk => clk,
miso => miso,
mosi => mosi,
sclk => sclk,
nsel => nsel,
wp => wp,
card => card,
led => led
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
phi0_process :process
begin
phi0 <= '1';
wait for clk_period/14;
phi0 <= '0';
wait for clk_period/14;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '1';
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;

179
VHDL/IO.vhd Normal file
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@ -0,0 +1,179 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:44:25 10/09/2017
-- Design Name:
-- Module Name: IO - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IO is
Port (
ADD_HIGH : in std_logic_vector(10 downto 8);
ADD_LOW : in std_logic_vector(1 downto 0);
B10 : out std_logic;
B9 : out std_logic;
B8 : out std_logic;
CARD : in std_logic;
DATA : inout std_logic_vector (7 downto 0);
CLK : in std_logic;
LED : out std_logic;
NDEV_SEL : in std_logic;
NG : out std_logic;
NIO_SEL : in std_logic;
NIO_STB : in std_logic;
NOE : out std_logic;
PHI0 : in std_logic;
NRESET : in std_logic;
RNW : in std_logic;
MISO : in std_logic;
MOSI : out std_logic;
NSEL : out std_logic;
SCLK : out std_logic;
WP : in std_logic
);
end IO;
architecture Behavioral of IO is
signal data_in : std_logic_vector (7 downto 0);
signal data_out : std_logic_vector (7 downto 0);
signal addr_low_int : std_logic_vector (1 downto 0);
signal wp_int : std_logic;
signal card_int : std_logic;
signal miso_int : std_logic;
signal ndev_sel_int : std_logic;
signal rnw_int : std_logic;
signal data_en : std_logic;
component AppleIISd is
Port (
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
is_read : in std_logic;
reset : in std_logic;
addr : in std_logic_vector (1 downto 0);
phi0 : in std_logic;
selected : in std_logic;
clk : in std_logic;
miso: in std_logic;
mosi : out std_logic;
sclk : out std_logic;
nsel : out std_logic;
wp : in std_logic;
card : in std_logic;
led : out std_logic
);
end component;
component AddressDecoder
port (
A8 : in std_logic;
A9 : in std_logic;
A10 : in std_logic;
NDEV_SEL : in std_logic;
NIO_SEL : in std_logic;
NIO_STB : in std_logic;
RNW : in std_logic;
B8 : out std_logic;
B9 : out std_logic;
B10 : out std_logic;
NOE : out std_logic;
NG : out std_logic;
DATA_EN : out std_logic
);
end component;
begin
spi: AppleIISd port map(
data_in => data_in,
data_out => data_out,
is_read => rnw_int,
reset => not NRESET,
addr => addr_low_int,
phi0 => PHI0,
selected => not ndev_sel_int,
clk => CLK,
miso => miso_int,
mosi => MOSI,
sclk => SCLK,
nsel => NSEL,
wp => wp_int,
card => card_int,
led => LED
);
addDec: AddressDecoder port map(
A8 => ADD_HIGH(8),
A9 => ADD_HIGH(9),
A10 => ADD_HIGH(10),
NDEV_SEL => NDEV_SEL,
NIO_SEL => NIO_SEL,
NIO_STB => NIO_STB,
RNW => RNW,
B8 => B8,
B9 => B9,
B10 => B10,
NOE => NOE,
NG => NG,
DATA_EN => data_en
);
ctrl_latch: process(CLK, NRESET)
begin
if(NRESET = '0') then
ndev_sel_int <= '1';
rnw_int <= '1';
wp_int <= '1';
card_int <= '1';
miso_int <= '1';
elsif rising_edge(CLK) then
ndev_sel_int <= NDEV_SEL;
rnw_int <= RNW;
wp_int <= WP;
card_int <= CARD;
miso_int <= MISO;
end if;
end process;
DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate
data_latch: process(ndev_sel)
begin
if(rising_edge(ndev_sel) and (rnw_int = '0')) then
data_in <= DATA;
end if;
end process;
add_latch: process(ndev_sel)
begin
if falling_edge(ndev_sel) then
addr_low_int <= ADD_LOW;
end if;
end process;
end Behavioral;

0
VHDL/io_buffers.tim
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2
VHDL/sch2HdlBatchFile
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@ -1 +1 @@
sch2hdl,-intstyle,ise,-family,xc9500xl,-verilog,U:/AppleIISd/VHDL/io_buffers.vf,-w,U:/AppleIISd/VHDL/io_buffers.sch
sch2hdl,-intstyle,ise,-family,xc9500xl,-flat,-suppress,-vhdl,U:/AppleIISd/VHDL/AddressDecoder.vhf,-w,U:/AppleIISd/VHDL/AddressDecoder.sch