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This commit is contained in:
freitz85 2017-10-10 22:55:21 +02:00
parent 7e2414c1bf
commit cc9d9d21db
14 changed files with 781 additions and 1514 deletions
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1
VHDL/AddressDecoder.jhd
View File

@ -1 +0,0 @@
MODULE AddressDecoder

48
VHDL/AddressDecoder.sym
View File

@ -1,48 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="AddressDecoder">
<symboltype>BLOCK</symboltype>
<timestamp>2017-10-8T19:38:25</timestamp>
<pin polarity="Input" x="0" y="-416" name="A10" />
<pin polarity="Input" x="0" y="-352" name="A9" />
<pin polarity="Input" x="0" y="-288" name="A8" />
<pin polarity="Input" x="0" y="-160" name="NIO_SEL" />
<pin polarity="Input" x="0" y="-32" name="NDEV_SEL" />
<pin polarity="Input" x="0" y="32" name="RNW" />
<pin polarity="Input" x="0" y="-96" name="NIO_STB" />
<pin polarity="Output" x="384" y="-416" name="B10" />
<pin polarity="Output" x="384" y="-288" name="B9" />
<pin polarity="Output" x="384" y="-160" name="B8" />
<pin polarity="Output" x="384" y="-32" name="NOE" />
<pin polarity="Output" x="384" y="96" name="NG" />
<pin polarity="Output" x="384" y="160" name="DATA_EN" />
<graph>
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-456" type="symbol" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-416" type="pin A10" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-352" type="pin A9" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-288" type="pin A8" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin NIO_SEL" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin NDEV_SEL" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="32" type="pin RNW" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin NIO_STB" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-416" type="pin B10" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-288" type="pin B9" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin B8" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin NOE" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="96" type="pin NG" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="160" type="pin DATA_EN" />
<line x2="384" y1="160" y2="160" x1="320" />
<line x2="384" y1="96" y2="96" x1="320" />
<line x2="0" y1="32" y2="32" x1="64" />
<line x2="0" y1="-416" y2="-416" x1="64" />
<line x2="0" y1="-352" y2="-352" x1="64" />
<line x2="0" y1="-288" y2="-288" x1="64" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<line x2="384" y1="-416" y2="-416" x1="320" />
<line x2="384" y1="-288" y2="-288" x1="320" />
<line x2="384" y1="-160" y2="-160" x1="320" />
<line x2="384" y1="-32" y2="-32" x1="320" />
<rect width="256" x="64" y="-448" height="640" />
</graph>
</symbol>

338
VHDL/IO.jed → VHDL/AppleIISd.jed
View File

@ -1,5 +1,5 @@
Programmer Jedec Bit Map
Date Extracted: Tue Oct 10 21:52:13 2017
Date Extracted: Tue Oct 10 22:56:58 2017
QF46656*
QP44*
@ -43,7 +43,7 @@ N PPMAP 21 6*
N PPMAP 24 7*
N PPMAP 26 8*
N PPMAP 27 9*
L0000000 00000000 00000000 00010000 00000000*
L0000000 00000000 00000000 00000000 00000000*
L0000032 00000000 00000000 00000000 00000000*
L0000064 00000000 00000000 00000000 00000000*
L0000096 00000000 00000000 00000000 00000000*
@ -53,7 +53,7 @@ L0000192 00000000 00000000 00000000 00000000*
L0000224 00000000 00000000 00000000 00000000*
L0000256 00000000 00000000 00000000 00000000*
L0000288 000000 000000 000000 000000*
L0000312 000000 000000 000000 000000*
L0000312 000000 000000 001000 000000*
L0000336 000000 000000 000000 000000*
L0000360 000000 000010 000000 000000*
L0000384 000000 000000 000000 000000*
@ -77,10 +77,10 @@ L0000864 00000000 00000000 00000000 00000000*
L0000896 00000000 00000000 00000000 00000000*
L0000928 00000000 00000000 00000000 00000000*
L0000960 00000000 00000000 00000000 00000000*
L0000992 00000000 00000000 00000000 00000000*
L0000992 00000000 10000000 00000000 00000000*
L0001024 00000000 00000000 00000000 00000000*
L0001056 00000000 00000000 00000000 00000000*
L0001088 00000000 10000000 00000000 00000000*
L0001088 00000000 00000000 00000000 00000000*
L0001120 00000010 00000000 00000000 00000000*
L0001152 000000 000000 000000 000000*
L0001176 000000 000000 000000 000000*
@ -110,14 +110,14 @@ L0001824 00000000 00000000 00000000 00000100*
L0001856 00000000 00000000 00000000 00000000*
L0001888 00000000 00000000 00000000 00000000*
L0001920 00000000 00000000 00000000 00000000*
L0001952 00000000 00000000 00000000 00000000*
L0001952 00000000 10000000 00000000 00000000*
L0001984 00000000 00000000 00000000 00000000*
L0002016 000000 000000 000000 000000*
L0002040 000000 000000 000000 000000*
L0002064 000000 000000 000000 000000*
L0002088 000000 000000 000000 000000*
L0002112 000000 000000 000000 000000*
L0002136 000000 100000 000000 000000*
L0002136 000000 000000 000000 000000*
L0002160 00000000 00000000 00000000 00000000*
L0002192 00000000 00000000 00000000 10000100*
L0002224 00000000 00000000 00000000 00000000*
@ -135,26 +135,26 @@ L0002544 000000 000000 000000 011110*
L0002568 000000 000000 000000 000000*
L0002592 00000010 00000000 00000000 00000000*
L0002624 00000000 00000000 00000000 00000000*
L0002656 00000001 00000000 00000000 00000000*
L0002656 00000000 00000000 00000000 00000000*
L0002688 00000010 00000000 00000000 00000000*
L0002720 00000010 00000000 00000000 00000000*
L0002752 00000000 00000000 00000000 00000000*
L0002784 00000011 10000000 00000000 00000000*
L0002816 00000011 00000000 00000000 00000000*
L0002752 00000011 00000000 00000000 00000000*
L0002784 00000000 00000000 00000000 00000000*
L0002816 00000000 00000000 00000000 00000000*
L0002848 00000000 00000000 00000000 00000000*
L0002880 000000 000000 000000 000000*
L0002904 000000 000000 000000 000000*
L0002928 000000 000000 000000 000000*
L0002952 000000 000000 000000 000000*
L0002976 000000 000000 000000 000000*
L0002976 000000 100000 000000 000000*
L0003000 000000 000000 000000 000000*
L0003024 11111100 00000000 00000100 00000000*
L0003056 00000001 00000000 00000000 00000000*
L0003024 11111110 00000000 00000100 00000000*
L0003056 00000011 00000000 00000000 00000000*
L0003088 00000000 00000000 00000000 00000000*
L0003120 00000000 00000000 00000000 00000000*
L0003152 00000000 00000000 00000000 00000000*
L0003152 00000010 00000000 00000000 00000000*
L0003184 11000001 00000000 00000000 10000000*
L0003216 00000000 00000000 00000000 00000000*
L0003216 00000011 00000000 00000000 00000000*
L0003248 00000000 00000000 00000000 00000000*
L0003280 00000000 00000000 00000000 00000000*
L0003312 000000 000000 000000 000000*
@ -214,24 +214,24 @@ L0004816 00000000 00000000 00000000 00000000*
L0004848 00000000 00000000 00000000 00000000*
L0004880 00000000 00000000 00000000 00000000*
L0004912 00000000 00000000 00000000 00000000*
L0004944 00000000 00000000 00000000 00000000*
L0004944 00000000 00000000 00010000 00000000*
L0004976 00000000 00000000 00000000 00000000*
L0005008 00000000 00000000 00000000 00000000*
L0005040 000000 000000 000000 000000*
L0005064 000000 000000 000000 000000*
L0005088 000000 000001 000100 100001*
L0005088 000000 000001 000000 100001*
L0005112 000000 000000 000000 000000*
L0005136 000000 000000 000000 000000*
L0005160 000000 000000 000000 000000*
L0005184 00000011 00000011 00000001 00000011*
L0005216 00000011 00000011 00000011 00000011*
L0005248 00000011 10000011 00000001 00000011*
L0005280 00000011 00000011 00000001 00000011*
L0005248 00000011 00000011 00000001 00000011*
L0005280 00000011 10000011 00000001 00000011*
L0005312 00000011 00000011 00000011 00000011*
L0005344 00000011 00000011 00000001 00000011*
L0005376 00000011 00000011 00000001 00000011*
L0005408 00000011 00000011 00000011 00000011*
L0005440 00000011 00000011 00000001 00000011*
L0005440 00000011 00000011 00000011 00000011*
L0005472 000000 000000 000000 000000*
L0005496 000000 000000 000000 000000*
L0005520 000000 000000 000000 000000*
@ -239,9 +239,9 @@ L0005544 000000 000000 000000 000000*
L0005568 000000 000000 000000 000000*
L0005592 000000 000000 000000 000000*
L0005616 00000011 00000011 00000000 00000011*
L0005648 00000010 00000011 00000000 01000001*
L0005648 00000010 00000011 00000001 01000001*
L0005680 00000011 00000011 00000001 00000011*
L0005712 00000011 00000011 00000001 00000011*
L0005712 00000011 00000011 00000000 00000011*
L0005744 00000010 00000011 00000001 00000000*
L0005776 00010001 00000010 00000001 00000011*
L0005808 00000011 00000011 00000001 00000011*
@ -254,7 +254,7 @@ L0005976 000000 000000 000000 000000*
L0006000 000000 000000 000000 000000*
L0006024 000000 000000 000000 000000*
L0006048 00000011 00000011 00000000 00000011*
L0006080 00000011 00000011 00000010 00000001*
L0006080 00000011 00000011 00000011 00000001*
L0006112 00000011 00000011 00000001 00000011*
L0006144 00000011 00000011 00000001 00000011*
L0006176 00000011 00000011 00000010 00000000*
@ -299,14 +299,14 @@ L0007272 000000 000000 000000 000000*
L0007296 000000 000000 000000 000000*
L0007320 000000 000000 000000 000000*
L0007344 00000011 00000010 00000000 00000011*
L0007376 00000010 00100000 00000000 00100001*
L0007376 00000010 00100000 00001000 00100001*
L0007408 00000011 00000010 00000000 00000011*
L0007440 00000011 00000000 00000000 00000011*
L0007472 00000010 00000000 00000000 00000000*
L0007504 00000001 00000000 00000000 00000011*
L0007536 00000011 00000001 00000001 00000011*
L0007568 00000000 00000001 00000000 00000001*
L0007600 00000001 00000001 00001000 00000011*
L0007600 00000001 00000001 00000000 00000011*
L0007632 000000 000000 000000 000000*
L0007656 000000 000000 000000 000000*
L0007680 100100 000000 000000 000000*
@ -315,7 +315,7 @@ L0007728 000000 000000 000000 000000*
L0007752 000000 000000 000000 000000*
L0007776 00000011 00000001 00000000 00000001*
L0007808 00000010 00000011 00000000 00000001*
L0007840 00000011 00000001 00000000 00000011*
L0007840 00000011 10000001 00000000 00000011*
L0007872 00000011 00000011 00000000 00000011*
L0007904 00000010 00000011 00000001 00000000*
L0007936 00000011 00000010 00000001 00000011*
@ -325,27 +325,27 @@ L0008032 00000011 00000011 00000001 00000011*
L0008064 000000 000000 000000 000000*
L0008088 000000 000000 000000 000000*
L0008112 000000 000000 000000 000000*
L0008136 000000 000000 000000 000000*
L0008160 000000 100000 000000 000000*
L0008136 000000 000000 000000 000001*
L0008160 000000 000000 000000 000000*
L0008184 000000 000000 000000 000000*
L0008208 00000001 00000011 00000000 00000001*
L0008240 01000010 00000011 00000000 00000001*
L0008240 00000010 00000011 00000000 00000001*
L0008272 00000011 00000011 00000000 00000011*
L0008304 00000011 00000011 00000000 00000010*
L0008336 00000010 00000011 00000001 00000000*
L0008368 00000001 00000010 00000001 00000010*
L0008400 00000011 00000011 00000001 00000010*
L0008432 00000000 00000011 00000000 00000000*
L0008432 00100000 00000011 00000000 00000000*
L0008464 00000001 00000011 00000001 00000011*
L0008496 000000 000000 000000 000000*
L0008520 000000 000000 000000 000000*
L0008544 000000 000000 000000 001000*
L0008544 000000 000000 000000 000000*
L0008568 000000 000000 000000 000000*
L0008592 000000 000000 000000 000000*
L0008616 000000 000000 000000 000000*
L0008640 00000000 00000000 00000000 00000000*
L0008672 00000000 00000010 00000000 00000000*
L0008704 00000000 00000000 00000000 00000000*
L0008704 00000000 00000000 00000000 01000000*
L0008736 00000000 00000000 00000000 00000000*
L0008768 00000000 00000000 00000000 00000000*
L0008800 00000000 00000000 00000000 00000000*
@ -355,23 +355,23 @@ L0008896 00000000 00000000 00000000 00000000*
L0008928 000000 000000 000000 000000*
L0008952 000000 000000 000000 000000*
L0008976 000000 000000 000000 000000*
L0009000 000000 000000 000000 000001*
L0009000 000000 000000 000000 100000*
L0009024 000000 000000 000000 000000*
L0009048 000000 000000 000000 000000*
L0009072 00000000 00000010 00000000 00000000*
L0009104 00001000 00000000 00000000 00000000*
L0009104 00001000 00000000 00001000 00000000*
L0009136 00000000 00000010 00000000 00000000*
L0009168 00000000 00000000 00000000 00000000*
L0009200 00000000 00000000 00000000 00000000*
L0009232 00000000 00000000 00000000 00000000*
L0009264 01000000 00000000 00000000 00000000*
L0009296 00000000 00000000 00000000 00000000*
L0009328 00000000 00000000 00001000 00000000*
L0009296 00000000 00000000 00000000 00010000*
L0009328 00000000 00000000 00000000 00000000*
L0009360 000000 000000 000000 000000*
L0009384 000000 000000 000000 000000*
L0009408 000010 000000 000000 000000*
L0009432 000000 000000 000000 000000*
L0009456 000000 000000 000000 000000*
L0009456 000000 000000 000000 000001*
L0009480 000000 000000 000000 000000*
L0009504 00000000 00000000 00000000 00000000*
L0009536 00000000 00000010 00000000 00000010*
@ -405,7 +405,7 @@ L0010320 000000 000000 000000 000001*
L0010344 000000 000000 000000 000000*
L0010368 00000000 00000000 00000000 00000000*
L0010400 00000000 00000010 00000000 00000000*
L0010432 00000000 00000000 00000000 01000000*
L0010432 00000000 00000000 00000000 00000000*
L0010464 00000000 00000000 00000000 00000000*
L0010496 00000000 00000000 00000000 00000000*
L0010528 00000000 00000000 00000000 00000000*
@ -415,33 +415,33 @@ L0010624 00000000 00000000 00000000 00000000*
L0010656 000000 000000 000000 000000*
L0010680 000000 000000 000000 000000*
L0010704 000000 000010 000000 000000*
L0010728 000000 000000 000000 100000*
L0010728 000000 000000 000000 000000*
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L0010776 000000 000000 000000 000000*
L0010800 00000000 00000000 00000000 00000000*
L0010832 00010000 00000000 00000000 00000000*
L0010832 00010000 00000000 00000000 10001000*
L0010864 00000000 00000010 00000000 00000000*
L0010896 00000000 00000000 00000000 00000000*
L0010928 00000000 00000000 00000000 00000000*
L0010960 00000000 00000000 00000100 00000000*
L0010960 00000000 00000000 00000000 00000000*
L0010992 00000000 00000000 00000000 00000000*
L0011024 00000000 00000000 00000000 00010000*
L0011024 00000000 00000000 00000000 00000000*
L0011056 00000000 00000000 00001000 00000000*
L0011088 000000 000000 000000 000000*
L0011112 000000 000010 000000 000000*
L0011136 000001 000000 000000 000000*
L0011160 000000 000000 000000 000000*
L0011184 000000 000000 000000 000001*
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L0011232 00000011 00000011 00000001 00000011*
L0011232 00000011 00000011 00010001 00000011*
L0011264 00000011 00000011 00000011 00000011*
L0011296 01110011 00000011 00000001 00000011*
L0011328 00001111 00000011 00000001 00000011*
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L0011392 00000011 00000011 00000001 10000011*
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L0012936 000000 000000 000000 000000*
L0012960 00000000 00000000 00000000 00000000*
L0012992 00000000 00000010 00000000 00000011*
L0013024 00000000 10000000 00000000 10111100*
L0013056 00000000 00000000 00000000 01000000*
L0013088 00000000 00000000 00000010 00000011*
L0013024 00000000 00000000 00000000 10111100*
L0013056 00000000 10000000 00000000 01000000*
L0013088 00000000 10000000 00000010 00000011*
L0013120 00000000 00000000 00000000 00000000*
L0013152 00000000 10000000 00000000 00000000*
L0013184 00000000 10000000 00000001 00000111*
L0013152 00000000 00000000 00000000 00000000*
L0013184 00000000 00000000 00000001 00000111*
L0013216 00000000 00000000 00000000 00010000*
L0013248 000000 100000 000000 000000*
L0013248 000000 000000 000000 000000*
L0013272 000000 000000 000000 000000*
L0013296 000000 000000 000000 000000*
L0013320 000000 000000 000000 011110*
L0013344 000000 000000 000000 100000*
L0013368 000000 000000 000000 000000*
L0013344 000000 100000 000000 100000*
L0013368 000000 100000 000000 000000*
L0013392 00000000 00000000 00000000 00000000*
L0013424 00000000 00000000 00000000 00000000*
L0013456 00000000 00000000 00000000 00000000*
L0013488 00000000 10000000 00000000 00000000*
L0013520 00000000 10000000 00000000 00000000*
L0013456 00000000 10000000 00000000 00000000*
L0013488 00000000 00000000 00000000 00000000*
L0013520 00000000 00000000 00000000 00000000*
L0013552 00100000 00000000 00000000 00000000*
L0013584 00000000 00000000 00000000 00000000*
L0013616 00000000 00000000 00000000 00000000*
L0013584 00000000 10000000 00000000 00000000*
L0013616 00000000 10000000 00000000 00000000*
L0013648 00000000 00000000 00100000 00000000*
L0013680 000000 000000 000000 000000*
L0013680 000000 100000 000000 000000*
L0013704 000000 000000 000000 000000*
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L0013752 000000 000000 000000 000000*
L0013776 000000 100000 000000 000000*
L0013800 000000 100000 000000 000000*
L0013776 000000 000000 000000 000000*
L0013800 000000 000000 000000 000000*
L0013824 00000000 00000000 00000001 00000000*
L0013856 00000001 00000000 00000011 00000010*
L0013856 00000001 00000000 00000010 00000010*
L0013888 00000000 00000000 00000000 00000000*
L0013920 00000000 00000000 00000000 00000000*
L0013920 00000000 00000000 00000001 00000000*
L0013952 00000001 00000000 00000010 00000011*
L0013984 00000010 00000001 00000000 00000000*
L0014016 00000000 00000000 00000000 00000000*
L0014048 00000011 00000000 00000011 00000010*
L0014080 00000010 00000000 00000000 00000000*
L0014080 00000010 00000000 00000010 00000000*
L0014112 000000 000000 000000 000000*
L0014136 000000 000000 000000 000000*
L0014160 000000 000000 000000 000000*
@ -539,9 +539,9 @@ L0014184 000000 000000 000000 000000*
L0014208 000000 000000 000000 000000*
L0014232 000000 000000 000000 000000*
L0014256 00000011 00000011 00000000 00000011*
L0014288 00000010 00000111 00000000 00000001*
L0014288 00000010 00000111 00000001 00000001*
L0014320 00000011 00000011 00000001 00000011*
L0014352 00000011 00000011 00000001 00000011*
L0014352 00000011 00000011 00000000 00000011*
L0014384 00000010 00000011 00000001 00000000*
L0014416 00000001 00000010 00000001 10000011*
L0014448 00111111 00000011 00000001 00000011*
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L0014640 000000 000000 000000 000000*
L0014664 000000 000000 000000 000000*
L0014688 00000011 00000011 00000000 00000011*
L0014720 00000010 00000011 00000000 00000001*
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L0014784 00000011 00000011 00000001 00000011*
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L0014816 00000010 00000011 00000001 00000000*
L0014848 00000001 00000010 00000001 00000011*
L0014880 00000011 00000011 00000001 00000011*
@ -677,7 +677,7 @@ L0018144 00000000 00000000 00000000 00000000*
L0018176 00000000 00000000 00000000 00000001*
L0018208 00000000 00000000 00000000 00000000*
L0018240 00000000 00000000 00000000 00000000*
L0018272 00000000 00000000 00000001 00000000*
L0018272 00000000 00000000 00000000 00000000*
L0018304 00000000 00000000 00000000 00000000*
L0018336 00000000 00000000 00000000 00000000*
L0018368 00000000 00000000 00000000 00000000*
@ -704,14 +704,14 @@ L0018936 000000 000000 000000 000000*
L0018960 000000 000000 000000 000000*
L0018984 000000 000000 000000 000000*
L0019008 00000000 00000000 00000000 00000000*
L0019040 00000001 00000010 00000010 00000011*
L0019040 00000001 00000010 00001010 00000011*
L0019072 00000000 00000000 00000000 00000000*
L0019104 00000000 00000000 00000000 00000000*
L0019136 00000001 00000000 00000010 00000011*
L0019168 00000010 00000000 00000100 11100000*
L0019200 00000000 00000000 01000000 00000000*
L0019232 00000011 00000000 00000011 00000011*
L0019264 00000010 00000000 00001000 00000000*
L0019264 00000010 00000000 00000000 00000000*
L0019296 000000 000000 000000 000000*
L0019320 000000 000000 000000 000000*
L0019344 000000 000000 000000 000000*
@ -726,7 +726,7 @@ L0019568 00000011 00000011 00000011 00000011*
L0019600 00000011 00000011 00000001 00000011*
L0019632 00000011 00000011 00000001 00000011*
L0019664 00000011 00000011 00000011 00000011*
L0019696 00000011 00000011 00000001 00000011*
L0019696 00000011 00000011 00000011 00000011*
L0019728 000000 000000 000000 000000*
L0019752 000000 000000 000000 000000*
L0019776 000000 000000 000000 000000*
@ -734,7 +734,7 @@ L0019800 000000 000000 000000 000000*
L0019824 000000 000000 000000 000000*
L0019848 000000 000000 000000 000000*
L0019872 00000011 00000011 00000000 00000011*
L0019904 00000011 00000011 00000010 00000001*
L0019904 00000011 00000011 00000011 00000001*
L0019936 00000011 00000011 00000001 00000011*
L0019968 00000011 00000011 00000001 00000011*
L0020000 00000011 00000011 00000010 00000000*
@ -763,7 +763,7 @@ L0020640 000000 000000 000000 000000*
L0020664 000000 000000 000000 000000*
L0020688 000000 000000 000000 000000*
L0020712 000000 000000 000000 000000*
L0020736 00000011 00000011 00000000 00000001*
L0020736 00000011 00000011 00001000 00000001*
L0020768 00000010 00000011 00000000 00000001*
L0020800 00001111 00000011 00000000 00000011*
L0020832 01110011 00000011 00000000 00000011*
@ -783,12 +783,12 @@ L0021200 00000000 00000010 00000000 00000000*
L0021232 00000000 00000010 00000000 00000000*
L0021264 00000000 00000000 00000000 00000000*
L0021296 00000000 00000000 00000000 00000000*
L0021328 00000000 00000000 00010000 00000000*
L0021328 00000000 00000000 00000000 00000000*
L0021360 00000000 00000000 00000000 00000000*
L0021392 00000001 00000000 00000000 00000000*
L0021424 00000000 00000000 00000000 00000000*
L0021456 000000 000000 000000 000000*
L0021480 000000 000000 000000 000000*
L0021480 000000 000000 001000 000000*
L0021504 000000 001000 000000 000000*
L0021528 000000 000000 000000 000000*
L0021552 000000 000000 000000 000000*
@ -826,38 +826,38 @@ L0022440 000000 000000 000000 000000*
L0022464 00000000 00000000 00000000 00000000*
L0022496 10000000 00000000 00000000 00000011*
L0022528 01110000 00000000 00000100 00000000*
L0022560 10001000 00000000 00000000 00000000*
L0022560 10000100 00000000 00000000 00000000*
L0022592 00000000 00000010 00000000 00000011*
L0022624 00011000 00000000 00000000 00000000*
L0022624 00110000 00000000 00000000 00000000*
L0022656 00000000 00000000 00000000 00000000*
L0022688 11101100 00000000 10100000 00000000*
L0022720 00000100 00000000 00100000 00000000*
L0022688 11101000 00000000 10000000 00000000*
L0022720 00000000 00000000 00100000 00000000*
L0022752 000001 000000 000000 000000*
L0022776 000000 000000 000000 000000*
L0022776 001000 000000 000000 000000*
L0022800 000000 000000 000000 000000*
L0022824 101000 000000 000000 000000*
L0022848 011100 000000 000000 000000*
L0022824 110000 000000 000000 000000*
L0022848 011011 000000 000000 000000*
L0022872 000000 000000 000000 000000*
L0022896 00000001 00000001 00000000 00000010*
L0022928 00000011 00000001 00000010 00000010*
L0022960 00000000 00000000 00000000 00000000*
L0022992 00000100 00000000 00000000 00000000*
L0022992 00001000 00000000 00000000 00000000*
L0023024 00000011 00000010 00000010 00000000*
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1DB3

57
VHDL/AppleIISd.sym
View File

@ -1,57 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="AppleIISd">
<symboltype>BLOCK</symboltype>
<timestamp>2017-10-8T19:42:44</timestamp>
<pin polarity="Input" x="0" y="-304" name="is_read" />
<pin polarity="Input" x="0" y="-240" name="reset" />
<pin polarity="Input" x="0" y="-816" name="phi0" />
<pin polarity="Input" x="0" y="-176" name="selected" />
<pin polarity="Input" x="0" y="-768" name="clk" />
<pin polarity="Input" x="0" y="-704" name="miso" />
<pin polarity="Input" x="0" y="-480" name="wp" />
<pin polarity="Input" x="0" y="-416" name="card" />
<pin polarity="Input" x="0" y="-112" name="data_in(7:0)" />
<pin polarity="Input" x="0" y="-368" name="addr(1:0)" />
<pin polarity="Output" x="384" y="-816" name="mosi" />
<pin polarity="Output" x="384" y="-752" name="sclk" />
<pin polarity="Output" x="384" y="-688" name="nsel" />
<pin polarity="Output" x="384" y="-560" name="led" />
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<graph>
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412
VHDL/AppleIISd.vhd
View File

@ -1,295 +1,187 @@
----------------------------------------------------------------------------------
-- Company: n/a
-- Engineer: A. Fachat
-- Company:
-- Engineer:
--
-- Create Date: 12:37:11 05/07/2011
-- Design Name: SPI65B
-- Module Name: SPI6502B - Behavioral
-- Project Name: CS/A NETUSB 2.0
-- Target Devices: CS/A NETUSB 2.0
-- Create Date: 20:44:25 10/09/2017
-- Design Name:
-- Module Name: IO - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: An SPI interface for 6502-based computers (or compatible).
-- modelled after the SPI65 interface by Daryl Rictor
-- (see http://sbc.rictor.org/io/65spi.html )
-- This implementation here, however, is a complete reimplementation
-- as the ABEL language of the original implementation is not supported
-- by ISE anymore.
-- Also I added the interrupt input handling, replacing four of the
-- original SPI select outputs with four interrupt inputs
-- Also folded out the single MISO input into one input for each of the
-- four supported devices, reducing external parts count again by one.
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - removed spiclk and replaced with clksrc and clkcnt_is_zero combination,
-- to drive up SPI clock to half of input clock (and not one fourth only as before)
-- unfortunately that costed one divisor bit to fit into the CPLD
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AppleIISd is
Port (
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0);
is_read : in STD_LOGIC;
nreset : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (1 downto 0);
phi0 : in STD_LOGIC;
ndev_sel : in STD_LOGIC;
clk : in STD_LOGIC;
miso: in std_logic;
mosi : out STD_LOGIC;
sclk : out STD_LOGIC;
nsel : out STD_LOGIC;
wp : in STD_LOGIC;
card : in STD_LOGIC;
led : out STD_LOGIC
ADD_HIGH : in std_logic_vector(10 downto 8);
ADD_LOW : in std_logic_vector(1 downto 0);
B : out std_logic_vector(10 downto 8);
CARD : in std_logic;
DATA : inout std_logic_vector (7 downto 0);
CLK : in std_logic;
LED : out std_logic;
NDEV_SEL : in std_logic;
NG : out std_logic;
NIO_SEL : in std_logic;
NIO_STB : in std_logic;
NOE : out std_logic;
PHI0 : in std_logic;
NRESET : in std_logic;
RNW : in std_logic;
MISO : in std_logic;
MOSI : out std_logic;
NSEL : out std_logic;
SCLK : out std_logic;
WP : in std_logic
-- synthesis translate_off
;
data_dbg : out std_logic_vector (7 downto 0);
add_dbg : out std_logic_vector (1 downto 0)
-- synthesis translate_on
);
constant DIV_WIDTH : integer := 3;
end AppleIISd;
architecture Behavioral of AppleIISd is
--------------------------
-- internal state
signal spidatain: std_logic_vector (7 downto 0);
signal spidataout: std_logic_vector (7 downto 0);
signal inited: std_logic; -- card initialized
-- spi register flags
signal tc: std_logic; -- transmission complete; cleared on spi data read
signal bsy: std_logic; -- SPI busy
signal frx: std_logic; -- fast receive mode
signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock
signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0);
signal slavesel: std_logic := '1'; -- slave select output (0=selected)
signal int_miso: std_logic;
--------------------------
-- helper signals
-- shift engine
signal start_shifting: std_logic := '0'; -- shifting data
signal shifting2: std_logic := '0'; -- shifting data
signal shiftdone: std_logic; -- shifting data done
signal shiftcnt: std_logic_vector(3 downto 0); -- shift counter (5 bit)
signal data_in : std_logic_vector (7 downto 0);
signal data_out : std_logic_vector (7 downto 0);
signal addr_low_int : std_logic_vector (1 downto 0);
signal wp_int : std_logic;
signal card_int : std_logic;
signal miso_int : std_logic;
-- spi clock
signal clksrc: std_logic; -- clock source (phi2 or clk_7m)
-- TODO divcnt is not used at all??
--signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter
signal shiftclk : std_logic;
begin
--led <= not (inited);
led <= not (bsy or not slavesel);
bsy <= start_shifting or shifting2;
process(start_shifting, shiftdone, shiftclk)
begin
if (rising_edge(shiftclk)) then
if (shiftdone = '1') then
shifting2 <= '0';
else
shifting2 <= start_shifting;
end if;
end if;
end process;
process(shiftcnt, nreset, shiftclk)
begin
if (nreset = '0') then
shiftdone <= '0';
elsif (rising_edge(shiftclk)) then
if (shiftcnt = "1111") then
shiftdone <= '1';
else
shiftdone <= '0';
end if;
end if;
end process;
process(nreset, shifting2, shiftcnt, shiftclk)
begin
if (nreset = '0') then
shiftcnt <= (others => '0');
elsif (rising_edge(shiftclk)) then
if (shifting2 = '1') then
-- count phase
shiftcnt <= shiftcnt + 1;
else
shiftcnt <= (others => '0');
end if;
end if;
end process;
inproc: process(nreset, shifting2, shiftcnt, shiftclk, spidatain, miso)
begin
if (nreset = '0') then
spidatain <= (others => '0');
elsif (rising_edge(shiftclk)) then
if (shifting2 = '1' and shiftcnt(0) = '1') then
-- shift in to input register
spidatain (7 downto 1) <= spidatain (6 downto 0);
spidatain (0) <= int_miso;
end if;
end if;
end process;
outproc: process(nreset, shifting2, spidataout, shiftcnt, shiftclk)
begin
if (nreset = '0') then
mosi <= '1';
sclk <= '0';
else
-- clock is sync'd
if (rising_edge(shiftclk)) then
if (shifting2='0' or shiftdone = '1') then
mosi <= '1';
sclk <= '0';
else
-- output data directly from output register
case shiftcnt(3 downto 1) is
when "000" => mosi <= spidataout(7);
when "001" => mosi <= spidataout(6);
when "010" => mosi <= spidataout(5);
when "011" => mosi <= spidataout(4);
when "100" => mosi <= spidataout(3);
when "101" => mosi <= spidataout(2);
when "110" => mosi <= spidataout(1);
when "111" => mosi <= spidataout(0);
when others => mosi <= '1';
end case;
sclk <= '0' xor '0' xor shiftcnt(0);
end if;
end if;
end if;
end process;
-- shift operation enable
shiften: process(nreset, ndev_sel, is_read, addr, frx, shiftdone)
begin
-- start shifting
if (nreset = '0' or shiftdone = '1') then
start_shifting <= '0';
elsif (rising_edge(ndev_sel) and addr="00" and (frx='1' or is_read='0')) then
-- access to register 00, either write (is_read=0) or fast receive bit set (frx)
-- then both types of access (write but also read)
start_shifting <= '1';
end if;
end process;
--------------------------
-- spiclk - spi clock generation
-- spiclk is still 2 times the freq. than sclk
clksrc <= phi0 when (ece = '0') else clk;
-- is a pulse signal to allow for divisor==0
--shiftclk <= clksrc when divcnt = "000000" else '0';
shiftclk <= clksrc when bsy = '1' else '0';
-- clkgen: process(nreset, divisor, clksrc)
-- begin
-- if (nreset = '0') then
-- divcnt <= divisor;
-- elsif (falling_edge(clksrc)) then
-- if (shiftclk = '1') then
-- divcnt <= divisor;
-- else
-- divcnt <= divcnt - 1;
-- end if;
-- end if;
-- end process;
--------------------------
-- interface section
-- inputs
int_miso <= (miso and not slavesel);
signal ndev_sel_int : std_logic;
signal rnw_int : std_logic;
signal data_en : std_logic;
-- outputs
nsel <= slavesel;
component SpiController is
Port (
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
is_read : in std_logic;
nreset : in std_logic;
addr : in std_logic_vector (1 downto 0);
phi0 : in std_logic;
ndev_sel : in std_logic;
clk : in std_logic;
miso: in std_logic;
mosi : out std_logic;
sclk : out std_logic;
nsel : out std_logic;
wp : in std_logic;
card : in std_logic;
led : out std_logic
);
end component;
tc_proc: process (ndev_sel, shiftdone)
component AddressDecoder
Port (
A : in std_logic_vector (10 downto 8);
B : out std_logic_vector (10 downto 8);
RNW : in std_logic;
NDEV_SEL : in std_logic;
NIO_SEL : in std_logic;
NIO_STB : in std_logic;
NRESET : in std_logic;
DATA_EN : out std_logic;
NG : out std_logic;
NOE : out std_logic
);
end component;
begin
spi: SpiController port map(
data_in => data_in,
data_out => data_out,
is_read => rnw_int,
nreset => NRESET,
addr => addr_low_int,
phi0 => PHI0,
ndev_sel => ndev_sel_int,
clk => CLK,
miso => miso_int,
mosi => MOSI,
sclk => SCLK,
nsel => NSEL,
wp => wp_int,
card => card_int,
led => LED
);
addDec: AddressDecoder port map(
A => ADD_HIGH,
B => B,
RNW => RNW,
NDEV_SEL => NDEV_SEL,
NIO_SEL => NIO_SEL,
NIO_STB => NIO_STB,
NRESET => NRESET,
DATA_EN => data_en,
NOE => NOE,
NG => NG
);
ctrl_latch: process(CLK, NRESET)
begin
if (shiftdone = '1') then
tc <= '1';
elsif (rising_edge(ndev_sel) and addr="00") then
tc <= '0';
if(NRESET = '0') then
ndev_sel_int <= '1';
rnw_int <= '1';
wp_int <= '1';
card_int <= '1';
miso_int <= '1';
elsif rising_edge(CLK) then
ndev_sel_int <= NDEV_SEL;
rnw_int <= RNW;
wp_int <= WP;
card_int <= CARD;
miso_int <= MISO;
end if;
end process;
--------------------------
-- cpu register section
-- cpu read
cpu_read: process(addr, spidatain, tc, bsy, frx,
ece, divisor, slavesel, wp, card, inited)
DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate
-- synthesis translate_off
--data_dbg <= data_in;
--add_dbg <= addr_low_int;
-- synthesis translate_on
data_latch: process(CLK)
begin
case addr is
when "00" => -- read SPI data in
data_out <= spidatain;
when "01" => -- read status register
data_out(0) <= '0';
data_out(1) <= '0';
data_out(2) <= ece;
data_out(3) <= '0';
data_out(4) <= frx;
data_out(5) <= bsy;
data_out(6) <= '0';
data_out(7) <= tc;
when "10" => -- read sclk divisor
data_out(DIV_WIDTH-1 downto 0) <= divisor;
data_out(7 downto 3) <= (others => '0');
when "11" => -- read slave select / slave interrupt state
data_out(0) <= slavesel;
data_out(4 downto 1) <= (others => '0');
data_out(5) <= wp;
data_out(6) <= card;
data_out(7) <= inited;
when others =>
data_out <= (others => '0');
end case;
end process;
-- cpu write
cpu_write: process(nreset, ndev_sel, is_read, addr, data_in, card, inited)
begin
if (nreset = '0') then
ece <= '0';
frx <= '0';
slavesel <= '1';
divisor <= (others => '0');
spidataout <= (others => '1');
inited <= '0';
elsif (card = '1') then
inited <= '0';
elsif (rising_edge(ndev_sel) and is_read = '0') then
case addr is
when "00" => -- write SPI data out (see other process above)
spidataout <= data_in;
when "01" => -- write status register
ece <= data_in(2);
frx <= data_in(4);
-- no bit 5 - 7
when "10" => -- write divisor
divisor <= data_in(DIV_WIDTH-1 downto 0);
when "11" => -- write slave select / slave interrupt enable
slavesel <= data_in(0);
-- no bit 1 - 6
inited <= data_in(7);
when others =>
end case;
--if(rising_edge(CLK) and NDEV_SEL = '0') and (RNW = '0')) then
--if rising_edge(CLK) and (NDEV_SEL = '0') then
if rising_edge(CLK) then
if (NDEV_SEL = '0') then
data_in <= DATA;
end if;
end if;
end process;
add_latch: process(NDEV_SEL)
begin
if falling_edge(NDEV_SEL) then
addr_low_int <= ADD_LOW;
end if;
end process;
end Behavioral;

30
VHDL/AppleIISd.xise
View File

@ -15,23 +15,23 @@
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="SpiController.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="IO.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="IO_Test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<file xil_pn:name="AppleIISd_Test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="AddressDecoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
</files>
@ -84,9 +84,9 @@
<property xil_pn:name="I/O Pin Termination" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|IO|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="IO.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/IO" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|AppleIISd|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="AppleIISd.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/AppleIISd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
@ -124,14 +124,14 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="IO" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="AppleIISd" xil_pn:valueState="default"/>
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="PC44" xil_pn:valueState="default"/>
<property xil_pn:name="Pipelining" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="IO_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="AppleIISd_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
@ -140,7 +140,7 @@
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="IO" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AppleIISd" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
@ -148,8 +148,8 @@
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/IO_Test/uut" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.IO" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AppleIISd_Test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AppleIISd_Test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
@ -159,7 +159,7 @@
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.IO" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AppleIISd_Test" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
@ -194,7 +194,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|IO|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AppleIISd_Test|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>

223
VHDL/AppleIISd_Test.vhd
View File

@ -2,15 +2,15 @@
-- Company:
-- Engineer:
--
-- Create Date: 20:21:20 10/09/2017
-- Create Date: 00:42:59 10/10/2017
-- Design Name:
-- Module Name: U:/AppleIISd/VHDL/AppleIISd_Test.vhd
-- Module Name: U:/AppleIISd/VHDL/IO_Test.vhd
-- Project Name: AppleIISd
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: AppleIISd
-- VHDL Test Bench Created by ISE for module: IO
--
-- Dependencies:
--
@ -41,107 +41,184 @@ ARCHITECTURE behavior OF AppleIISd_Test IS
COMPONENT AppleIISd
PORT(
data_in : IN std_logic_vector(7 downto 0);
data_out : OUT std_logic_vector(7 downto 0);
is_read : IN std_logic;
reset : IN std_logic;
addr : IN std_logic_vector(1 downto 0);
phi0 : IN std_logic;
selected : IN std_logic;
clk : IN std_logic;
miso : IN std_logic;
mosi : OUT std_logic;
sclk : OUT std_logic;
nsel : OUT std_logic;
wp : IN std_logic;
card : IN std_logic;
led : OUT std_logic
ADD_HIGH : IN std_logic_vector(10 downto 8);
ADD_LOW : IN std_logic_vector(1 downto 0);
B : OUT std_logic_vector(10 downto 8);
CARD : IN std_logic;
DATA : INOUT std_logic_vector(7 downto 0);
CLK : IN std_logic;
LED : OUT std_logic;
NDEV_SEL : IN std_logic;
NG : OUT std_logic;
NIO_SEL : IN std_logic;
NIO_STB : IN std_logic;
NOE : OUT std_logic;
PHI0 : IN std_logic;
NRESET : IN std_logic;
RNW : IN std_logic;
MISO : IN std_logic;
MOSI : OUT std_logic;
NSEL : OUT std_logic;
SCLK : OUT std_logic;
WP : IN std_logic;
data_dbg : out std_logic_vector (7 downto 0);
add_dbg : out std_logic_vector (1 downto 0)
);
END COMPONENT;
--Inputs
signal data_in : std_logic_vector(7 downto 0) := (others => '1');
signal is_read : std_logic := '0';
signal reset : std_logic := '0';
signal addr : std_logic_vector(1 downto 0) := (others => '0');
signal phi0 : std_logic := '1';
signal selected : std_logic := '0';
signal clk : std_logic := '0';
signal miso : std_logic := '0';
signal wp : std_logic := '0';
signal card : std_logic := '0';
signal ADD_HIGH : std_logic_vector(10 downto 8) := (others => 'U');
signal ADD_LOW : std_logic_vector(1 downto 0) := (others => 'U');
signal CARD : std_logic := '0';
signal CLK : std_logic := '0';
signal NDEV_SEL : std_logic := '1';
signal NIO_SEL : std_logic := '1';
signal NIO_STB : std_logic := '1';
signal PHI0 : std_logic := '0';
signal NRESET : std_logic := '1';
signal RNW : std_logic := '1';
signal MISO : std_logic := '1';
signal WP : std_logic := '0';
--BiDirs
signal DATA : std_logic_vector(7 downto 0) := (others => 'Z');
--Outputs
signal data_out : std_logic_vector(7 downto 0);
signal mosi : std_logic;
signal sclk : std_logic;
signal nsel : std_logic;
signal led : std_logic;
signal B : std_logic_vector(10 downto 8);
signal LED : std_logic;
signal NG : std_logic;
signal NOE : std_logic;
signal MOSI : std_logic;
signal NSEL : std_logic;
signal SCLK : std_logic;
signal data_dbg : std_logic_vector (7 downto 0);
signal add_dbg : std_logic_vector (1 downto 0);
-- Clock period definitions
constant clk_period : time := 142 ns; -- 7MHz
constant CLK_period : time := 142 ns;
-- Bus timings
-- worst case
constant ADD_valid : time := 300 ns; -- II+
constant DATA_valid : time := 200 ns; -- II+
constant ADD_hold : time := 15 ns; -- IIgs
--best case
--constant ADD_valid : time := 100 ns; -- IIgs
--constant DATA_valid : time := 30 ns; -- IIgs
--constant ADD_hold : time := 15 ns; -- IIgs
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: AppleIISd PORT MAP (
data_in => data_in,
data_out => data_out,
is_read => is_read,
reset => reset,
addr => addr,
phi0 => phi0,
selected => selected,
clk => clk,
miso => miso,
mosi => mosi,
sclk => sclk,
nsel => nsel,
wp => wp,
card => card,
led => led
ADD_HIGH => ADD_HIGH,
ADD_LOW => ADD_LOW,
B => B,
CARD => CARD,
DATA => DATA,
CLK => CLK,
LED => LED,
NDEV_SEL => NDEV_SEL,
NG => NG,
NIO_SEL => NIO_SEL,
NIO_STB => NIO_STB,
NOE => NOE,
PHI0 => PHI0,
NRESET => NRESET,
RNW => RNW,
MISO => MISO,
MOSI => MOSI,
NSEL => NSEL,
SCLK => SCLK,
WP => WP,
data_dbg => data_dbg,
add_dbg => add_dbg
);
-- Clock process definitions
clk_process :process
CLK_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
phi0_process :process(clk)
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
PHI0_process :process(CLK)
variable counter : integer range 0 to 7;
begin
if rising_edge(clk) or falling_edge(clk) then
if rising_edge(CLK) or falling_edge(CLK) then
counter := counter + 1;
if counter = 7 then
phi0 <= not phi0;
PHI0 <= not PHI0;
counter := 0;
end if;
end if;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state.
wait for clk_period * 20;
reset <= '1';
wait for clk_period * 20;
reset <= '0';
wait for clk_period * 5;
wait until rising_edge(phi0);
-- insert stimulus here
selected <= '1';
wait for clk_period;
data_in <= (others => '0');
wait until falling_edge(phi0);
selected <= '0';
wait for clk_period;
data_in <= (others => '1');
wait for CLK_period * 20;
NRESET <= '0';
wait for CLK_period * 20;
NRESET <= '1';
wait for CLK_period * 10;
-- read reg 0
DATA <= (others => 'Z');
ADD_LOW <= (others => 'U');
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '0');
RNW <= '1';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
DATA <= (others => 'Z');
wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait for ADD_hold;
ADD_LOW <= (others => 'U');
-- read reg 3
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '1');
RNW <= '1';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
DATA <= (others => 'Z');
wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait for ADD_hold;
ADD_LOW <= (others => 'U');
-- send data
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '0');
RNW <= '0';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
DATA <= (others => 'Z');
wait for DATA_valid;
DATA <= (others => '0');
wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait for ADD_hold;
wait for CLK_period;
ADD_LOW <= (others => 'U');
RNW <= '1';
DATA <= (others => 'Z');
wait;
end process;

187
VHDL/IO.vhd
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@ -1,187 +0,0 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:44:25 10/09/2017
-- Design Name:
-- Module Name: IO - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IO is
Port (
ADD_HIGH : in std_logic_vector(10 downto 8);
ADD_LOW : in std_logic_vector(1 downto 0);
B : out std_logic_vector(10 downto 8);
CARD : in std_logic;
DATA : inout std_logic_vector (7 downto 0);
CLK : in std_logic;
LED : out std_logic;
NDEV_SEL : in std_logic;
NG : out std_logic;
NIO_SEL : in std_logic;
NIO_STB : in std_logic;
NOE : out std_logic;
PHI0 : in std_logic;
NRESET : in std_logic;
RNW : in std_logic;
MISO : in std_logic;
MOSI : out std_logic;
NSEL : out std_logic;
SCLK : out std_logic;
WP : in std_logic
-- synthesis translate_off
;
data_dbg : out std_logic_vector (7 downto 0);
add_dbg : out std_logic_vector (1 downto 0)
-- synthesis translate_on
);
end IO;
architecture Behavioral of IO is
signal data_in : std_logic_vector (7 downto 0);
signal data_out : std_logic_vector (7 downto 0);
signal addr_low_int : std_logic_vector (1 downto 0);
signal wp_int : std_logic;
signal card_int : std_logic;
signal miso_int : std_logic;
signal ndev_sel_int : std_logic;
signal rnw_int : std_logic;
signal data_en : std_logic;
component AppleIISd is
Port (
data_in : in std_logic_vector (7 downto 0);
data_out : out std_logic_vector (7 downto 0);
is_read : in std_logic;
nreset : in std_logic;
addr : in std_logic_vector (1 downto 0);
phi0 : in std_logic;
ndev_sel : in std_logic;
clk : in std_logic;
miso: in std_logic;
mosi : out std_logic;
sclk : out std_logic;
nsel : out std_logic;
wp : in std_logic;
card : in std_logic;
led : out std_logic
);
end component;
component AddressDecoder
Port (
A : in std_logic_vector (10 downto 8);
B : out std_logic_vector (10 downto 8);
RNW : in std_logic;
NDEV_SEL : in std_logic;
NIO_SEL : in std_logic;
NIO_STB : in std_logic;
NRESET : in std_logic;
DATA_EN : out std_logic;
NG : out std_logic;
NOE : out std_logic
);
end component;
begin
spi: AppleIISd port map(
data_in => data_in,
data_out => data_out,
is_read => rnw_int,
nreset => NRESET,
addr => addr_low_int,
phi0 => PHI0,
ndev_sel => ndev_sel_int,
clk => CLK,
miso => miso_int,
mosi => MOSI,
sclk => SCLK,
nsel => NSEL,
wp => wp_int,
card => card_int,
led => LED
);
addDec: AddressDecoder port map(
A => ADD_HIGH,
B => B,
RNW => RNW,
NDEV_SEL => NDEV_SEL,
NIO_SEL => NIO_SEL,
NIO_STB => NIO_STB,
NRESET => NRESET,
DATA_EN => data_en,
NOE => NOE,
NG => NG
);
ctrl_latch: process(CLK, NRESET)
begin
if(NRESET = '0') then
ndev_sel_int <= '1';
rnw_int <= '1';
wp_int <= '1';
card_int <= '1';
miso_int <= '1';
elsif rising_edge(CLK) then
ndev_sel_int <= NDEV_SEL;
rnw_int <= RNW;
wp_int <= WP;
card_int <= CARD;
miso_int <= MISO;
end if;
end process;
DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate
-- synthesis translate_off
--data_dbg <= data_in;
--add_dbg <= addr_low_int;
-- synthesis translate_on
data_latch: process(CLK)
begin
--if(rising_edge(CLK) and NDEV_SEL = '0') and (RNW = '0')) then
--if rising_edge(CLK) and (NDEV_SEL = '0') then
if rising_edge(CLK) then
if (NDEV_SEL = '0') then
data_in <= DATA;
end if;
end if;
end process;
add_latch: process(NDEV_SEL)
begin
if falling_edge(NDEV_SEL) then
addr_low_int <= ADD_LOW;
end if;
end process;
end Behavioral;

225
VHDL/IO_Test.vhd
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@ -1,225 +0,0 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:42:59 10/10/2017
-- Design Name:
-- Module Name: U:/AppleIISd/VHDL/IO_Test.vhd
-- Project Name: AppleIISd
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: IO
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY IO_Test IS
END IO_Test;
ARCHITECTURE behavior OF IO_Test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IO
PORT(
ADD_HIGH : IN std_logic_vector(10 downto 8);
ADD_LOW : IN std_logic_vector(1 downto 0);
B : OUT std_logic_vector(10 downto 8);
CARD : IN std_logic;
DATA : INOUT std_logic_vector(7 downto 0);
CLK : IN std_logic;
LED : OUT std_logic;
NDEV_SEL : IN std_logic;
NG : OUT std_logic;
NIO_SEL : IN std_logic;
NIO_STB : IN std_logic;
NOE : OUT std_logic;
PHI0 : IN std_logic;
NRESET : IN std_logic;
RNW : IN std_logic;
MISO : IN std_logic;
MOSI : OUT std_logic;
NSEL : OUT std_logic;
SCLK : OUT std_logic;
WP : IN std_logic;
data_dbg : out std_logic_vector (7 downto 0);
add_dbg : out std_logic_vector (1 downto 0)
);
END COMPONENT;
--Inputs
signal ADD_HIGH : std_logic_vector(10 downto 8) := (others => 'U');
signal ADD_LOW : std_logic_vector(1 downto 0) := (others => 'U');
signal CARD : std_logic := '0';
signal CLK : std_logic := '0';
signal NDEV_SEL : std_logic := '1';
signal NIO_SEL : std_logic := '1';
signal NIO_STB : std_logic := '1';
signal PHI0 : std_logic := '0';
signal NRESET : std_logic := '1';
signal RNW : std_logic := '1';
signal MISO : std_logic := '1';
signal WP : std_logic := '0';
--BiDirs
signal DATA : std_logic_vector(7 downto 0) := (others => 'Z');
--Outputs
signal B : std_logic_vector(10 downto 8);
signal LED : std_logic;
signal NG : std_logic;
signal NOE : std_logic;
signal MOSI : std_logic;
signal NSEL : std_logic;
signal SCLK : std_logic;
signal data_dbg : std_logic_vector (7 downto 0);
signal add_dbg : std_logic_vector (1 downto 0);
-- Clock period definitions
constant CLK_period : time := 142 ns;
-- Bus timings
-- worst case
constant ADD_valid : time := 300 ns; -- II+
constant DATA_valid : time := 200 ns; -- II+
constant ADD_hold : time := 15 ns; -- IIgs
--best case
--constant ADD_valid : time := 100 ns; -- IIgs
--constant DATA_valid : time := 30 ns; -- IIgs
--constant ADD_hold : time := 15 ns; -- IIgs
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: IO PORT MAP (
ADD_HIGH => ADD_HIGH,
ADD_LOW => ADD_LOW,
B => B,
CARD => CARD,
DATA => DATA,
CLK => CLK,
LED => LED,
NDEV_SEL => NDEV_SEL,
NG => NG,
NIO_SEL => NIO_SEL,
NIO_STB => NIO_STB,
NOE => NOE,
PHI0 => PHI0,
NRESET => NRESET,
RNW => RNW,
MISO => MISO,
MOSI => MOSI,
NSEL => NSEL,
SCLK => SCLK,
WP => WP,
data_dbg => data_dbg,
add_dbg => add_dbg
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
PHI0_process :process(CLK)
variable counter : integer range 0 to 7;
begin
if rising_edge(CLK) or falling_edge(CLK) then
counter := counter + 1;
if counter = 7 then
PHI0 <= not PHI0;
counter := 0;
end if;
end if;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state.
wait for CLK_period * 20;
NRESET <= '0';
wait for CLK_period * 20;
NRESET <= '1';
wait for CLK_period * 10;
-- read reg 0
DATA <= (others => 'Z');
ADD_LOW <= (others => 'U');
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '0');
RNW <= '1';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
DATA <= (others => 'Z');
wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait for ADD_hold;
ADD_LOW <= (others => 'U');
-- read reg 3
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '1');
RNW <= '1';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
DATA <= (others => 'Z');
wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait for ADD_hold;
ADD_LOW <= (others => 'U');
-- send data
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '0');
RNW <= '0';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
DATA <= (others => 'Z');
wait for DATA_valid;
DATA <= (others => '0');
wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait for ADD_hold;
--wait for CLK_period;
ADD_LOW <= (others => 'U');
RNW <= '1';
DATA <= (others => 'Z');
wait;
end process;
END;

295
VHDL/SpiController.vhd Normal file
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----------------------------------------------------------------------------------
-- Company: n/a
-- Engineer: A. Fachat
--
-- Create Date: 12:37:11 05/07/2011
-- Design Name: SPI65B
-- Module Name: SPI6502B - Behavioral
-- Project Name: CS/A NETUSB 2.0
-- Target Devices: CS/A NETUSB 2.0
-- Tool versions:
-- Description: An SPI interface for 6502-based computers (or compatible).
-- modelled after the SPI65 interface by Daryl Rictor
-- (see http://sbc.rictor.org/io/65spi.html )
-- This implementation here, however, is a complete reimplementation
-- as the ABEL language of the original implementation is not supported
-- by ISE anymore.
-- Also I added the interrupt input handling, replacing four of the
-- original SPI select outputs with four interrupt inputs
-- Also folded out the single MISO input into one input for each of the
-- four supported devices, reducing external parts count again by one.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - removed spiclk and replaced with clksrc and clkcnt_is_zero combination,
-- to drive up SPI clock to half of input clock (and not one fourth only as before)
-- unfortunately that costed one divisor bit to fit into the CPLD
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SpiController is
Port (
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0);
is_read : in STD_LOGIC;
nreset : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (1 downto 0);
phi0 : in STD_LOGIC;
ndev_sel : in STD_LOGIC;
clk : in STD_LOGIC;
miso: in std_logic;
mosi : out STD_LOGIC;
sclk : out STD_LOGIC;
nsel : out STD_LOGIC;
wp : in STD_LOGIC;
card : in STD_LOGIC;
led : out STD_LOGIC
);
constant DIV_WIDTH : integer := 3;
end SpiController;
architecture Behavioral of SpiController is
--------------------------
-- internal state
signal spidatain: std_logic_vector (7 downto 0);
signal spidataout: std_logic_vector (7 downto 0);
signal inited: std_logic; -- card initialized
-- spi register flags
signal tc: std_logic; -- transmission complete; cleared on spi data read
signal bsy: std_logic; -- SPI busy
signal frx: std_logic; -- fast receive mode
signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock
signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0);
signal slavesel: std_logic := '1'; -- slave select output (0=selected)
signal int_miso: std_logic;
--------------------------
-- helper signals
-- shift engine
signal start_shifting: std_logic := '0'; -- shifting data
signal shifting2: std_logic := '0'; -- shifting data
signal shiftdone: std_logic; -- shifting data done
signal shiftcnt: std_logic_vector(3 downto 0); -- shift counter (5 bit)
-- spi clock
signal clksrc: std_logic; -- clock source (phi2 or clk_7m)
-- TODO divcnt is not used at all??
--signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter
signal shiftclk : std_logic;
begin
--led <= not (inited);
led <= not (bsy or not slavesel);
bsy <= start_shifting or shifting2;
process(start_shifting, shiftdone, shiftclk)
begin
if (rising_edge(shiftclk)) then
if (shiftdone = '1') then
shifting2 <= '0';
else
shifting2 <= start_shifting;
end if;
end if;
end process;
process(shiftcnt, nreset, shiftclk)
begin
if (nreset = '0') then
shiftdone <= '0';
elsif (rising_edge(shiftclk)) then
if (shiftcnt = "1111") then
shiftdone <= '1';
else
shiftdone <= '0';
end if;
end if;
end process;
process(nreset, shifting2, shiftcnt, shiftclk)
begin
if (nreset = '0') then
shiftcnt <= (others => '0');
elsif (rising_edge(shiftclk)) then
if (shifting2 = '1') then
-- count phase
shiftcnt <= shiftcnt + 1;
else
shiftcnt <= (others => '0');
end if;
end if;
end process;
inproc: process(nreset, shifting2, shiftcnt, shiftclk, spidatain, miso)
begin
if (nreset = '0') then
spidatain <= (others => '0');
elsif (rising_edge(shiftclk)) then
if (shifting2 = '1' and shiftcnt(0) = '1') then
-- shift in to input register
spidatain (7 downto 1) <= spidatain (6 downto 0);
spidatain (0) <= int_miso;
end if;
end if;
end process;
outproc: process(nreset, shifting2, spidataout, shiftcnt, shiftclk)
begin
if (nreset = '0') then
mosi <= '1';
sclk <= '0';
else
-- clock is sync'd
if (rising_edge(shiftclk)) then
if (shifting2='0' or shiftdone = '1') then
mosi <= '1';
sclk <= '0';
else
-- output data directly from output register
case shiftcnt(3 downto 1) is
when "000" => mosi <= spidataout(7);
when "001" => mosi <= spidataout(6);
when "010" => mosi <= spidataout(5);
when "011" => mosi <= spidataout(4);
when "100" => mosi <= spidataout(3);
when "101" => mosi <= spidataout(2);
when "110" => mosi <= spidataout(1);
when "111" => mosi <= spidataout(0);
when others => mosi <= '1';
end case;
sclk <= '0' xor '0' xor shiftcnt(0);
end if;
end if;
end if;
end process;
-- shift operation enable
shiften: process(nreset, ndev_sel, is_read, addr, frx, shiftdone)
begin
-- start shifting
if (nreset = '0' or shiftdone = '1') then
start_shifting <= '0';
elsif (rising_edge(ndev_sel) and addr="00" and (frx='1' or is_read='0')) then
-- access to register 00, either write (is_read=0) or fast receive bit set (frx)
-- then both types of access (write but also read)
start_shifting <= '1';
end if;
end process;
--------------------------
-- spiclk - spi clock generation
-- spiclk is still 2 times the freq. than sclk
clksrc <= phi0 when (ece = '0') else clk;
-- is a pulse signal to allow for divisor==0
--shiftclk <= clksrc when divcnt = "000000" else '0';
shiftclk <= clksrc when bsy = '1' else '0';
-- clkgen: process(nreset, divisor, clksrc)
-- begin
-- if (nreset = '0') then
-- divcnt <= divisor;
-- elsif (falling_edge(clksrc)) then
-- if (shiftclk = '1') then
-- divcnt <= divisor;
-- else
-- divcnt <= divcnt - 1;
-- end if;
-- end if;
-- end process;
--------------------------
-- interface section
-- inputs
int_miso <= (miso and not slavesel);
-- outputs
nsel <= slavesel;
tc_proc: process (ndev_sel, shiftdone)
begin
if (shiftdone = '1') then
tc <= '1';
elsif (rising_edge(ndev_sel) and addr="00") then
tc <= '0';
end if;
end process;
--------------------------
-- cpu register section
-- cpu read
cpu_read: process(addr, spidatain, tc, bsy, frx,
ece, divisor, slavesel, wp, card, inited)
begin
case addr is
when "00" => -- read SPI data in
data_out <= spidatain;
when "01" => -- read status register
data_out(0) <= '0';
data_out(1) <= '0';
data_out(2) <= ece;
data_out(3) <= '0';
data_out(4) <= frx;
data_out(5) <= bsy;
data_out(6) <= '0';
data_out(7) <= tc;
when "10" => -- read sclk divisor
data_out(DIV_WIDTH-1 downto 0) <= divisor;
data_out(7 downto 3) <= (others => '0');
when "11" => -- read slave select / slave interrupt state
data_out(0) <= slavesel;
data_out(4 downto 1) <= (others => '0');
data_out(5) <= wp;
data_out(6) <= card;
data_out(7) <= inited;
when others =>
data_out <= (others => '0');
end case;
end process;
-- cpu write
cpu_write: process(nreset, ndev_sel, is_read, addr, data_in, card, inited)
begin
if (nreset = '0') then
ece <= '0';
frx <= '0';
slavesel <= '1';
divisor <= (others => '0');
spidataout <= (others => '1');
inited <= '0';
elsif (card = '1') then
inited <= '0';
elsif (rising_edge(ndev_sel) and is_read = '0') then
case addr is
when "00" => -- write SPI data out (see other process above)
spidataout <= data_in;
when "01" => -- write status register
ece <= data_in(2);
frx <= data_in(4);
-- no bit 5 - 7
when "10" => -- write divisor
divisor <= data_in(DIV_WIDTH-1 downto 0);
when "11" => -- write slave select / slave interrupt enable
slavesel <= data_in(0);
-- no bit 1 - 6
inited <= data_in(7);
when others =>
end case;
end if;
end process;
end Behavioral;

1
VHDL/in_buf.jhd
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@ -1 +0,0 @@
MODULE in_buf

12
VHDL/in_buf.sch
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@ -1,12 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<drawing version="7">
<attr value="xc9500xl" name="DeviceFamilyName">
<trait delete="all:0" />
<trait editname="all:0" />
<trait edittrait="all:0" />
</attr>
<netlist>
</netlist>
<sheet sheetnum="1" width="3520" height="2720">
</sheet>
</drawing>

466
VHDL/io_buffers.sch
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@ -1,466 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<drawing version="7">
<attr value="xc9500xl" name="DeviceFamilyName">
<trait delete="all:0" />
<trait editname="all:0" />
<trait edittrait="all:0" />
</attr>
<netlist>
<signal name="NIO_SEL" />
<signal name="DATA(7:0)" />
<signal name="CLK" />
<signal name="RNW" />
<signal name="XLXN_52(7:0)" />
<signal name="XLXN_56" />
<signal name="NIO_STB" />
<signal name="NDEV_SEL" />
<signal name="XLXN_65" />
<signal name="XLXN_66" />
<signal name="XLXN_77" />
<signal name="XLXN_78" />
<signal name="XLXN_79" />
<signal name="XLXN_84" />
<signal name="A8" />
<signal name="A9" />
<signal name="A10" />
<signal name="PHI0" />
<signal name="MISO" />
<signal name="A0" />
<signal name="A1" />
<signal name="CARD" />
<signal name="WP" />
<signal name="add(1:0)" />
<signal name="add(0)" />
<signal name="add(1)" />
<signal name="XLXN_100" />
<signal name="XLXN_101" />
<signal name="NRESET" />
<signal name="XLXN_105(7:0)" />
<signal name="B10" />
<signal name="B9" />
<signal name="B8" />
<signal name="NOE" />
<signal name="NG" />
<signal name="MOSI" />
<signal name="SCLK" />
<signal name="NSEL" />
<signal name="XLXN_126" />
<signal name="XLXN_128" />
<signal name="XLXN_129" />
<signal name="XLXN_131" />
<signal name="LED" />
<port polarity="Input" name="NIO_SEL" />
<port polarity="BiDirectional" name="DATA(7:0)" />
<port polarity="Input" name="CLK" />
<port polarity="Input" name="RNW" />
<port polarity="Input" name="NIO_STB" />
<port polarity="Input" name="NDEV_SEL" />
<port polarity="Input" name="A8" />
<port polarity="Input" name="A9" />
<port polarity="Input" name="A10" />
<port polarity="Input" name="PHI0" />
<port polarity="Input" name="MISO" />
<port polarity="Input" name="A0" />
<port polarity="Input" name="A1" />
<port polarity="Input" name="CARD" />
<port polarity="Input" name="WP" />
<port polarity="Input" name="NRESET" />
<port polarity="Output" name="B10" />
<port polarity="Output" name="B9" />
<port polarity="Output" name="B8" />
<port polarity="Output" name="NOE" />
<port polarity="Output" name="NG" />
<port polarity="Output" name="MOSI" />
<port polarity="Output" name="SCLK" />
<port polarity="Output" name="NSEL" />
<port polarity="Output" name="LED" />
<blockdef name="ld4">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-448" y2="-448" x1="0" />
<line x2="64" y1="-384" y2="-384" x1="0" />
<line x2="64" y1="-320" y2="-320" x1="0" />
<line x2="64" y1="-256" y2="-256" x1="0" />
<line x2="320" y1="-448" y2="-448" x1="384" />
<line x2="320" y1="-384" y2="-384" x1="384" />
<line x2="320" y1="-320" y2="-320" x1="384" />
<line x2="320" y1="-256" y2="-256" x1="384" />
<line x2="64" y1="-128" y2="-128" x1="0" />
<rect width="256" x="64" y="-512" height="448" />
</blockdef>
<blockdef name="ld8">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-256" y2="-256" x1="0" />
<line x2="320" y1="-256" y2="-256" x1="384" />
<rect width="256" x="64" y="-320" height="256" />
<rect width="64" x="320" y="-268" height="24" />
<rect width="64" x="0" y="-268" height="24" />
<line x2="64" y1="-128" y2="-128" x1="0" />
</blockdef>
<blockdef name="bufe8">
<timestamp>2000-1-1T10:10:10</timestamp>
<rect width="96" x="128" y="-44" height="24" />
<line x2="64" y1="-32" y2="-32" x1="0" />
<line x2="64" y1="-96" y2="-96" x1="0" />
<line x2="64" y1="-64" y2="0" x1="64" />
<line x2="64" y1="-32" y2="-64" x1="128" />
<line x2="128" y1="0" y2="-32" x1="64" />
<rect width="64" x="0" y="-44" height="24" />
<line x2="128" y1="-32" y2="-32" x1="224" />
<line x2="64" y1="-96" y2="-96" x1="96" />
<line x2="96" y1="-48" y2="-96" x1="96" />
</blockdef>
<blockdef name="AddressDecoder">
<timestamp>2017-10-8T19:38:25</timestamp>
<line x2="384" y1="160" y2="160" x1="320" />
<line x2="384" y1="96" y2="96" x1="320" />
<line x2="0" y1="32" y2="32" x1="64" />
<line x2="0" y1="-416" y2="-416" x1="64" />
<line x2="0" y1="-352" y2="-352" x1="64" />
<line x2="0" y1="-288" y2="-288" x1="64" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<line x2="384" y1="-416" y2="-416" x1="320" />
<line x2="384" y1="-288" y2="-288" x1="320" />
<line x2="384" y1="-160" y2="-160" x1="320" />
<line x2="384" y1="-32" y2="-32" x1="320" />
<rect width="256" x="64" y="-448" height="640" />
</blockdef>
<blockdef name="AppleIISd">
<timestamp>2017-10-8T19:42:44</timestamp>
<line x2="0" y1="-480" y2="-480" x1="64" />
<line x2="0" y1="-416" y2="-416" x1="64" />
<rect width="256" x="64" y="-896" height="860" />
<line x2="64" y1="-816" y2="-816" x1="0" />
<line x2="0" y1="-304" y2="-304" x1="64" />
<line x2="0" y1="-240" y2="-240" x1="64" />
<line x2="0" y1="-176" y2="-176" x1="64" />
<rect width="64" x="0" y="-124" height="24" />
<line x2="0" y1="-112" y2="-112" x1="64" />
<rect width="64" x="0" y="-380" height="24" />
<line x2="0" y1="-368" y2="-368" x1="64" />
<line x2="0" y1="-768" y2="-768" x1="64" />
<line x2="0" y1="-704" y2="-704" x1="64" />
<line x2="384" y1="-752" y2="-752" x1="320" />
<line x2="384" y1="-688" y2="-688" x1="320" />
<line x2="384" y1="-816" y2="-816" x1="320" />
<rect width="64" x="320" y="-524" height="24" />
<line x2="384" y1="-512" y2="-512" x1="320" />
<line x2="384" y1="-560" y2="-560" x1="320" />
</blockdef>
<blockdef name="inv">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-32" y2="-32" x1="0" />
<line x2="160" y1="-32" y2="-32" x1="224" />
<line x2="128" y1="-64" y2="-32" x1="64" />
<line x2="64" y1="-32" y2="0" x1="128" />
<line x2="64" y1="0" y2="-64" x1="64" />
<circle r="16" cx="144" cy="-32" />
</blockdef>
<block symbolname="ld8" name="XLXI_2">
<blockpin signalname="DATA(7:0)" name="D(7:0)" />
<blockpin signalname="CLK" name="G" />
<blockpin signalname="XLXN_105(7:0)" name="Q(7:0)" />
</block>
<block symbolname="bufe8" name="XLXI_8">
<blockpin signalname="XLXN_56" name="E" />
<blockpin signalname="XLXN_52(7:0)" name="I(7:0)" />
<blockpin signalname="DATA(7:0)" name="O(7:0)" />
</block>
<block symbolname="AddressDecoder" name="XLXI_11">
<blockpin signalname="XLXN_79" name="A10" />
<blockpin signalname="XLXN_78" name="A9" />
<blockpin signalname="XLXN_77" name="A8" />
<blockpin signalname="XLXN_65" name="NIO_SEL" />
<blockpin signalname="XLXN_84" name="NDEV_SEL" />
<blockpin signalname="XLXN_128" name="RNW" />
<blockpin signalname="XLXN_66" name="NIO_STB" />
<blockpin signalname="B10" name="B10" />
<blockpin signalname="B9" name="B9" />
<blockpin signalname="B8" name="B8" />
<blockpin signalname="NOE" name="NOE" />
<blockpin signalname="NG" name="NG" />
<blockpin signalname="XLXN_56" name="DATA_EN" />
</block>
<block symbolname="AppleIISd" name="XLXI_17">
<blockpin signalname="XLXN_128" name="is_read" />
<blockpin signalname="XLXN_126" name="reset" />
<blockpin signalname="PHI0" name="phi0" />
<blockpin signalname="XLXN_129" name="selected" />
<blockpin signalname="CLK" name="clk" />
<blockpin signalname="XLXN_131" name="miso" />
<blockpin signalname="XLXN_101" name="wp" />
<blockpin signalname="XLXN_100" name="card" />
<blockpin signalname="XLXN_105(7:0)" name="data_in(7:0)" />
<blockpin signalname="add(1:0)" name="addr(1:0)" />
<blockpin signalname="MOSI" name="mosi" />
<blockpin signalname="SCLK" name="sclk" />
<blockpin signalname="NSEL" name="nsel" />
<blockpin signalname="LED" name="led" />
<blockpin signalname="XLXN_52(7:0)" name="data_out(7:0)" />
</block>
<block symbolname="ld4" name="XLXI_3">
<blockpin signalname="NIO_SEL" name="D0" />
<blockpin signalname="NIO_STB" name="D1" />
<blockpin signalname="NDEV_SEL" name="D2" />
<blockpin signalname="RNW" name="D3" />
<blockpin signalname="CLK" name="G" />
<blockpin signalname="XLXN_65" name="Q0" />
<blockpin signalname="XLXN_66" name="Q1" />
<blockpin signalname="XLXN_84" name="Q2" />
<blockpin signalname="XLXN_128" name="Q3" />
</block>
<block symbolname="ld4" name="XLXI_21">
<blockpin signalname="WP" name="D0" />
<blockpin signalname="CARD" name="D1" />
<blockpin signalname="A1" name="D2" />
<blockpin signalname="A0" name="D3" />
<blockpin signalname="CLK" name="G" />
<blockpin signalname="XLXN_101" name="Q0" />
<blockpin signalname="XLXN_100" name="Q1" />
<blockpin signalname="add(1)" name="Q2" />
<blockpin signalname="add(0)" name="Q3" />
</block>
<block symbolname="ld4" name="XLXI_22">
<blockpin signalname="MISO" name="D0" />
<blockpin signalname="A10" name="D1" />
<blockpin signalname="A9" name="D2" />
<blockpin signalname="A8" name="D3" />
<blockpin signalname="CLK" name="G" />
<blockpin signalname="XLXN_131" name="Q0" />
<blockpin signalname="XLXN_79" name="Q1" />
<blockpin signalname="XLXN_78" name="Q2" />
<blockpin signalname="XLXN_77" name="Q3" />
</block>
<block symbolname="inv" name="XLXI_23">
<blockpin signalname="XLXN_84" name="I" />
<blockpin signalname="XLXN_129" name="O" />
</block>
<block symbolname="inv" name="XLXI_24">
<blockpin signalname="NRESET" name="I" />
<blockpin signalname="XLXN_126" name="O" />
</block>
</netlist>
<sheet sheetnum="1" width="3520" height="2720">
<instance x="656" y="528" name="XLXI_2" orien="R0" />
<iomarker fontsize="28" x="224" y="400" name="CLK" orien="R180" />
<branch name="NIO_SEL">
<wire x2="656" y1="1808" y2="1808" x1="528" />
</branch>
<branch name="DATA(7:0)">
<wire x2="608" y1="272" y2="272" x1="560" />
<wire x2="656" y1="272" y2="272" x1="608" />
<wire x2="608" y1="144" y2="272" x1="608" />
<wire x2="2800" y1="144" y2="144" x1="608" />
<wire x2="2800" y1="144" y2="624" x1="2800" />
<wire x2="2800" y1="624" y2="624" x1="2736" />
</branch>
<iomarker fontsize="28" x="560" y="272" name="DATA(7:0)" orien="R180" />
<branch name="CLK">
<wire x2="304" y1="400" y2="400" x1="224" />
<wire x2="656" y1="400" y2="400" x1="304" />
<wire x2="304" y1="400" y2="528" x1="304" />
<wire x2="304" y1="528" y2="944" x1="304" />
<wire x2="304" y1="944" y2="1472" x1="304" />
<wire x2="656" y1="1472" y2="1472" x1="304" />
<wire x2="304" y1="1472" y2="1648" x1="304" />
<wire x2="304" y1="1648" y2="2128" x1="304" />
<wire x2="656" y1="2128" y2="2128" x1="304" />
<wire x2="656" y1="944" y2="944" x1="304" />
<wire x2="1904" y1="528" y2="528" x1="304" />
<wire x2="2000" y1="368" y2="368" x1="1904" />
<wire x2="1904" y1="368" y2="528" x1="1904" />
</branch>
<branch name="RNW">
<wire x2="656" y1="2000" y2="2000" x1="528" />
</branch>
<branch name="XLXN_56">
<wire x2="2512" y1="2128" y2="2128" x1="1808" />
<wire x2="2512" y1="688" y2="2128" x1="2512" />
</branch>
<branch name="NIO_STB">
<wire x2="656" y1="1872" y2="1872" x1="528" />
</branch>
<branch name="NDEV_SEL">
<wire x2="656" y1="1936" y2="1936" x1="528" />
</branch>
<branch name="XLXN_66">
<wire x2="1424" y1="1872" y2="1872" x1="1040" />
</branch>
<instance x="656" y="1600" name="XLXI_22" orien="R0" />
<branch name="XLXN_78">
<wire x2="1216" y1="1280" y2="1280" x1="1040" />
<wire x2="1216" y1="1280" y2="1616" x1="1216" />
<wire x2="1424" y1="1616" y2="1616" x1="1216" />
</branch>
<branch name="XLXN_79">
<wire x2="1248" y1="1216" y2="1216" x1="1040" />
<wire x2="1248" y1="1216" y2="1552" x1="1248" />
<wire x2="1424" y1="1552" y2="1552" x1="1248" />
</branch>
<instance x="1328" y="1328" name="XLXI_23" orien="R0" />
<branch name="XLXN_84">
<wire x2="1312" y1="1936" y2="1936" x1="1040" />
<wire x2="1424" y1="1936" y2="1936" x1="1312" />
<wire x2="1328" y1="1296" y2="1296" x1="1312" />
<wire x2="1312" y1="1296" y2="1936" x1="1312" />
</branch>
<instance x="656" y="1072" name="XLXI_21" orien="R0" />
<branch name="A8">
<wire x2="656" y1="1344" y2="1344" x1="624" />
</branch>
<iomarker fontsize="28" x="624" y="1344" name="A8" orien="R180" />
<branch name="A9">
<wire x2="656" y1="1280" y2="1280" x1="624" />
</branch>
<iomarker fontsize="28" x="624" y="1280" name="A9" orien="R180" />
<branch name="A10">
<wire x2="656" y1="1216" y2="1216" x1="624" />
</branch>
<iomarker fontsize="28" x="624" y="1216" name="A10" orien="R180" />
<branch name="PHI0">
<wire x2="2000" y1="320" y2="320" x1="1776" />
</branch>
<branch name="MISO">
<wire x2="656" y1="1152" y2="1152" x1="624" />
</branch>
<iomarker fontsize="28" x="624" y="1152" name="MISO" orien="R180" />
<branch name="A0">
<wire x2="656" y1="816" y2="816" x1="624" />
</branch>
<iomarker fontsize="28" x="624" y="816" name="A0" orien="R180" />
<branch name="A1">
<wire x2="656" y1="752" y2="752" x1="624" />
</branch>
<iomarker fontsize="28" x="624" y="752" name="A1" orien="R180" />
<branch name="CARD">
<wire x2="656" y1="688" y2="688" x1="624" />
</branch>
<iomarker fontsize="28" x="624" y="688" name="CARD" orien="R180" />
<branch name="WP">
<wire x2="656" y1="624" y2="624" x1="624" />
</branch>
<iomarker fontsize="28" x="624" y="624" name="WP" orien="R180" />
<bustap x2="1168" y1="752" y2="752" x1="1264" />
<bustap x2="1168" y1="816" y2="816" x1="1264" />
<branch name="add(0)">
<wire x2="1168" y1="816" y2="816" x1="1040" />
</branch>
<branch name="add(1)">
<wire x2="1168" y1="752" y2="752" x1="1040" />
</branch>
<instance x="1552" y="1264" name="XLXI_24" orien="R0" />
<iomarker fontsize="28" x="1536" y="1232" name="NRESET" orien="R180" />
<branch name="NRESET">
<wire x2="1552" y1="1232" y2="1232" x1="1536" />
</branch>
<branch name="XLXN_105(7:0)">
<wire x2="1600" y1="272" y2="272" x1="1040" />
<wire x2="1600" y1="272" y2="1024" x1="1600" />
<wire x2="2000" y1="1024" y2="1024" x1="1600" />
</branch>
<instance x="2000" y="1136" name="XLXI_17" orien="R0">
</instance>
<branch name="XLXN_101">
<wire x2="1056" y1="624" y2="624" x1="1040" />
<wire x2="1056" y1="624" y2="656" x1="1056" />
<wire x2="2000" y1="656" y2="656" x1="1056" />
</branch>
<branch name="XLXN_100">
<wire x2="1056" y1="688" y2="688" x1="1040" />
<wire x2="1056" y1="688" y2="720" x1="1056" />
<wire x2="2000" y1="720" y2="720" x1="1056" />
</branch>
<branch name="add(1:0)">
<wire x2="1264" y1="752" y2="768" x1="1264" />
<wire x2="1264" y1="768" y2="816" x1="1264" />
<wire x2="2000" y1="768" y2="768" x1="1264" />
</branch>
<instance x="656" y="2256" name="XLXI_3" orien="R0" />
<branch name="XLXN_65">
<wire x2="1424" y1="1808" y2="1808" x1="1040" />
</branch>
<iomarker fontsize="28" x="528" y="1936" name="NDEV_SEL" orien="R180" />
<iomarker fontsize="28" x="528" y="1872" name="NIO_STB" orien="R180" />
<iomarker fontsize="28" x="528" y="1808" name="NIO_SEL" orien="R180" />
<iomarker fontsize="28" x="528" y="2000" name="RNW" orien="R180" />
<instance x="1424" y="1968" name="XLXI_11" orien="R0">
</instance>
<branch name="XLXN_77">
<wire x2="1184" y1="1344" y2="1344" x1="1040" />
<wire x2="1184" y1="1344" y2="1680" x1="1184" />
<wire x2="1424" y1="1680" y2="1680" x1="1184" />
</branch>
<branch name="B10">
<wire x2="1840" y1="1552" y2="1552" x1="1808" />
</branch>
<iomarker fontsize="28" x="1840" y="1552" name="B10" orien="R0" />
<branch name="B9">
<wire x2="1840" y1="1680" y2="1680" x1="1808" />
</branch>
<iomarker fontsize="28" x="1840" y="1680" name="B9" orien="R0" />
<branch name="B8">
<wire x2="1840" y1="1808" y2="1808" x1="1808" />
</branch>
<iomarker fontsize="28" x="1840" y="1808" name="B8" orien="R0" />
<branch name="NOE">
<wire x2="1840" y1="1936" y2="1936" x1="1808" />
</branch>
<iomarker fontsize="28" x="1840" y="1936" name="NOE" orien="R0" />
<branch name="NG">
<wire x2="1840" y1="2064" y2="2064" x1="1808" />
</branch>
<iomarker fontsize="28" x="1840" y="2064" name="NG" orien="R0" />
<iomarker fontsize="28" x="1776" y="320" name="PHI0" orien="R180" />
<branch name="XLXN_126">
<wire x2="1888" y1="1232" y2="1232" x1="1776" />
<wire x2="2000" y1="896" y2="896" x1="1888" />
<wire x2="1888" y1="896" y2="1232" x1="1888" />
</branch>
<branch name="XLXN_128">
<wire x2="1280" y1="2000" y2="2000" x1="1040" />
<wire x2="1424" y1="2000" y2="2000" x1="1280" />
<wire x2="1280" y1="1168" y2="2000" x1="1280" />
<wire x2="1680" y1="1168" y2="1168" x1="1280" />
<wire x2="2000" y1="832" y2="832" x1="1680" />
<wire x2="1680" y1="832" y2="1168" x1="1680" />
</branch>
<branch name="XLXN_129">
<wire x2="1792" y1="1296" y2="1296" x1="1552" />
<wire x2="1792" y1="960" y2="1296" x1="1792" />
<wire x2="2000" y1="960" y2="960" x1="1792" />
</branch>
<branch name="XLXN_131">
<wire x2="1520" y1="1152" y2="1152" x1="1040" />
<wire x2="1520" y1="592" y2="1152" x1="1520" />
<wire x2="1936" y1="592" y2="592" x1="1520" />
<wire x2="2000" y1="432" y2="432" x1="1936" />
<wire x2="1936" y1="432" y2="592" x1="1936" />
</branch>
<branch name="NSEL">
<wire x2="2400" y1="448" y2="448" x1="2384" />
<wire x2="2416" y1="448" y2="448" x1="2400" />
<wire x2="2448" y1="448" y2="448" x1="2416" />
</branch>
<branch name="SCLK">
<wire x2="2400" y1="384" y2="384" x1="2384" />
<wire x2="2448" y1="384" y2="384" x1="2400" />
</branch>
<branch name="MOSI">
<wire x2="2400" y1="320" y2="320" x1="2384" />
<wire x2="2448" y1="320" y2="320" x1="2400" />
</branch>
<instance x="2512" y="592" name="XLXI_8" orien="M180" />
<branch name="XLXN_52(7:0)">
<wire x2="2512" y1="624" y2="624" x1="2384" />
</branch>
<iomarker fontsize="28" x="2448" y="448" name="NSEL" orien="R0" />
<iomarker fontsize="28" x="2448" y="384" name="SCLK" orien="R0" />
<iomarker fontsize="28" x="2448" y="320" name="MOSI" orien="R0" />
<branch name="LED">
<wire x2="2400" y1="576" y2="576" x1="2384" />
<wire x2="2448" y1="576" y2="576" x1="2400" />
</branch>
<iomarker fontsize="28" x="2448" y="576" name="LED" orien="R0" />
</sheet>
</drawing>

0
VHDL/sch2HdlBatchFile
View File