From cc9d9d21dbb8195bb38b69745003d2f6c0bc99de Mon Sep 17 00:00:00 2001 From: freitz85 Date: Tue, 10 Oct 2017 22:55:21 +0200 Subject: [PATCH] Rename files --- VHDL/AddressDecoder.jhd | 1 - VHDL/AddressDecoder.sym | 48 ---- VHDL/{IO.jed => AppleIISd.jed} | 338 ++++++++++++------------ VHDL/AppleIISd.sym | 57 ---- VHDL/AppleIISd.vhd | 412 +++++++++++------------------ VHDL/AppleIISd.xise | 30 +-- VHDL/AppleIISd_Test.vhd | 223 ++++++++++------ VHDL/IO.vhd | 187 ------------- VHDL/IO_Test.vhd | 225 ---------------- VHDL/SpiController.vhd | 295 +++++++++++++++++++++ VHDL/in_buf.jhd | 1 - VHDL/in_buf.sch | 12 - VHDL/io_buffers.sch | 466 --------------------------------- VHDL/sch2HdlBatchFile | 0 14 files changed, 781 insertions(+), 1514 deletions(-) delete mode 100644 VHDL/AddressDecoder.jhd delete mode 100644 VHDL/AddressDecoder.sym rename VHDL/{IO.jed => AppleIISd.jed} (89%) delete mode 100644 VHDL/AppleIISd.sym delete mode 100644 VHDL/IO.vhd delete mode 100644 VHDL/IO_Test.vhd create mode 100644 VHDL/SpiController.vhd delete mode 100644 VHDL/in_buf.jhd delete mode 100644 VHDL/in_buf.sch delete mode 100644 VHDL/io_buffers.sch delete mode 100644 VHDL/sch2HdlBatchFile diff --git a/VHDL/AddressDecoder.jhd b/VHDL/AddressDecoder.jhd deleted file mode 100644 index 021f01f..0000000 --- a/VHDL/AddressDecoder.jhd +++ /dev/null @@ -1 +0,0 @@ -MODULE AddressDecoder diff --git a/VHDL/AddressDecoder.sym b/VHDL/AddressDecoder.sym deleted file mode 100644 index 7a34ba0..0000000 --- a/VHDL/AddressDecoder.sym +++ /dev/null @@ -1,48 +0,0 @@ - - - BLOCK - 2017-10-8T19:38:25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/VHDL/IO.jed b/VHDL/AppleIISd.jed similarity index 89% rename from VHDL/IO.jed rename to VHDL/AppleIISd.jed index e377102..876fec5 100644 --- a/VHDL/IO.jed +++ b/VHDL/AppleIISd.jed @@ -1,5 +1,5 @@ Programmer Jedec Bit Map -Date Extracted: Tue Oct 10 21:52:13 2017 +Date Extracted: Tue Oct 10 22:56:58 2017 QF46656* QP44* @@ -43,7 +43,7 @@ N PPMAP 21 6* N PPMAP 24 7* N PPMAP 26 8* N PPMAP 27 9* -L0000000 00000000 00000000 00010000 00000000* +L0000000 00000000 00000000 00000000 00000000* L0000032 00000000 00000000 00000000 00000000* L0000064 00000000 00000000 00000000 00000000* L0000096 00000000 00000000 00000000 00000000* @@ -53,7 +53,7 @@ L0000192 00000000 00000000 00000000 00000000* L0000224 00000000 00000000 00000000 00000000* L0000256 00000000 00000000 00000000 00000000* L0000288 000000 000000 000000 000000* -L0000312 000000 000000 000000 000000* +L0000312 000000 000000 001000 000000* L0000336 000000 000000 000000 000000* L0000360 000000 000010 000000 000000* L0000384 000000 000000 000000 000000* @@ -77,10 +77,10 @@ L0000864 00000000 00000000 00000000 00000000* L0000896 00000000 00000000 00000000 00000000* L0000928 00000000 00000000 00000000 00000000* L0000960 00000000 00000000 00000000 00000000* -L0000992 00000000 00000000 00000000 00000000* +L0000992 00000000 10000000 00000000 00000000* L0001024 00000000 00000000 00000000 00000000* L0001056 00000000 00000000 00000000 00000000* -L0001088 00000000 10000000 00000000 00000000* +L0001088 00000000 00000000 00000000 00000000* L0001120 00000010 00000000 00000000 00000000* L0001152 000000 000000 000000 000000* L0001176 000000 000000 000000 000000* @@ -110,14 +110,14 @@ L0001824 00000000 00000000 00000000 00000100* L0001856 00000000 00000000 00000000 00000000* L0001888 00000000 00000000 00000000 00000000* L0001920 00000000 00000000 00000000 00000000* -L0001952 00000000 00000000 00000000 00000000* +L0001952 00000000 10000000 00000000 00000000* L0001984 00000000 00000000 00000000 00000000* L0002016 000000 000000 000000 000000* L0002040 000000 000000 000000 000000* L0002064 000000 000000 000000 000000* L0002088 000000 000000 000000 000000* L0002112 000000 000000 000000 000000* -L0002136 000000 100000 000000 000000* +L0002136 000000 000000 000000 000000* L0002160 00000000 00000000 00000000 00000000* L0002192 00000000 00000000 00000000 10000100* L0002224 00000000 00000000 00000000 00000000* @@ -135,26 +135,26 @@ L0002544 000000 000000 000000 011110* L0002568 000000 000000 000000 000000* L0002592 00000010 00000000 00000000 00000000* L0002624 00000000 00000000 00000000 00000000* -L0002656 00000001 00000000 00000000 00000000* +L0002656 00000000 00000000 00000000 00000000* L0002688 00000010 00000000 00000000 00000000* L0002720 00000010 00000000 00000000 00000000* -L0002752 00000000 00000000 00000000 00000000* -L0002784 00000011 10000000 00000000 00000000* -L0002816 00000011 00000000 00000000 00000000* +L0002752 00000011 00000000 00000000 00000000* +L0002784 00000000 00000000 00000000 00000000* +L0002816 00000000 00000000 00000000 00000000* L0002848 00000000 00000000 00000000 00000000* L0002880 000000 000000 000000 000000* L0002904 000000 000000 000000 000000* L0002928 000000 000000 000000 000000* L0002952 000000 000000 000000 000000* -L0002976 000000 000000 000000 000000* +L0002976 000000 100000 000000 000000* L0003000 000000 000000 000000 000000* -L0003024 11111100 00000000 00000100 00000000* -L0003056 00000001 00000000 00000000 00000000* +L0003024 11111110 00000000 00000100 00000000* +L0003056 00000011 00000000 00000000 00000000* L0003088 00000000 00000000 00000000 00000000* L0003120 00000000 00000000 00000000 00000000* -L0003152 00000000 00000000 00000000 00000000* +L0003152 00000010 00000000 00000000 00000000* L0003184 11000001 00000000 00000000 10000000* -L0003216 00000000 00000000 00000000 00000000* +L0003216 00000011 00000000 00000000 00000000* L0003248 00000000 00000000 00000000 00000000* L0003280 00000000 00000000 00000000 00000000* L0003312 000000 000000 000000 000000* @@ -214,24 +214,24 @@ L0004816 00000000 00000000 00000000 00000000* L0004848 00000000 00000000 00000000 00000000* L0004880 00000000 00000000 00000000 00000000* L0004912 00000000 00000000 00000000 00000000* -L0004944 00000000 00000000 00000000 00000000* +L0004944 00000000 00000000 00010000 00000000* L0004976 00000000 00000000 00000000 00000000* L0005008 00000000 00000000 00000000 00000000* L0005040 000000 000000 000000 000000* L0005064 000000 000000 000000 000000* -L0005088 000000 000001 000100 100001* +L0005088 000000 000001 000000 100001* L0005112 000000 000000 000000 000000* L0005136 000000 000000 000000 000000* L0005160 000000 000000 000000 000000* L0005184 00000011 00000011 00000001 00000011* L0005216 00000011 00000011 00000011 00000011* -L0005248 00000011 10000011 00000001 00000011* -L0005280 00000011 00000011 00000001 00000011* +L0005248 00000011 00000011 00000001 00000011* +L0005280 00000011 10000011 00000001 00000011* L0005312 00000011 00000011 00000011 00000011* L0005344 00000011 00000011 00000001 00000011* L0005376 00000011 00000011 00000001 00000011* L0005408 00000011 00000011 00000011 00000011* -L0005440 00000011 00000011 00000001 00000011* +L0005440 00000011 00000011 00000011 00000011* L0005472 000000 000000 000000 000000* L0005496 000000 000000 000000 000000* L0005520 000000 000000 000000 000000* @@ -239,9 +239,9 @@ L0005544 000000 000000 000000 000000* L0005568 000000 000000 000000 000000* L0005592 000000 000000 000000 000000* L0005616 00000011 00000011 00000000 00000011* -L0005648 00000010 00000011 00000000 01000001* +L0005648 00000010 00000011 00000001 01000001* L0005680 00000011 00000011 00000001 00000011* -L0005712 00000011 00000011 00000001 00000011* +L0005712 00000011 00000011 00000000 00000011* L0005744 00000010 00000011 00000001 00000000* L0005776 00010001 00000010 00000001 00000011* L0005808 00000011 00000011 00000001 00000011* @@ -254,7 +254,7 @@ L0005976 000000 000000 000000 000000* L0006000 000000 000000 000000 000000* L0006024 000000 000000 000000 000000* L0006048 00000011 00000011 00000000 00000011* -L0006080 00000011 00000011 00000010 00000001* +L0006080 00000011 00000011 00000011 00000001* L0006112 00000011 00000011 00000001 00000011* L0006144 00000011 00000011 00000001 00000011* L0006176 00000011 00000011 00000010 00000000* @@ -299,14 +299,14 @@ L0007272 000000 000000 000000 000000* L0007296 000000 000000 000000 000000* L0007320 000000 000000 000000 000000* L0007344 00000011 00000010 00000000 00000011* -L0007376 00000010 00100000 00000000 00100001* +L0007376 00000010 00100000 00001000 00100001* L0007408 00000011 00000010 00000000 00000011* L0007440 00000011 00000000 00000000 00000011* L0007472 00000010 00000000 00000000 00000000* L0007504 00000001 00000000 00000000 00000011* L0007536 00000011 00000001 00000001 00000011* L0007568 00000000 00000001 00000000 00000001* -L0007600 00000001 00000001 00001000 00000011* +L0007600 00000001 00000001 00000000 00000011* L0007632 000000 000000 000000 000000* L0007656 000000 000000 000000 000000* L0007680 100100 000000 000000 000000* @@ -315,7 +315,7 @@ L0007728 000000 000000 000000 000000* L0007752 000000 000000 000000 000000* L0007776 00000011 00000001 00000000 00000001* L0007808 00000010 00000011 00000000 00000001* -L0007840 00000011 00000001 00000000 00000011* +L0007840 00000011 10000001 00000000 00000011* L0007872 00000011 00000011 00000000 00000011* L0007904 00000010 00000011 00000001 00000000* L0007936 00000011 00000010 00000001 00000011* @@ -325,27 +325,27 @@ L0008032 00000011 00000011 00000001 00000011* L0008064 000000 000000 000000 000000* L0008088 000000 000000 000000 000000* L0008112 000000 000000 000000 000000* -L0008136 000000 000000 000000 000000* -L0008160 000000 100000 000000 000000* +L0008136 000000 000000 000000 000001* +L0008160 000000 000000 000000 000000* L0008184 000000 000000 000000 000000* L0008208 00000001 00000011 00000000 00000001* -L0008240 01000010 00000011 00000000 00000001* +L0008240 00000010 00000011 00000000 00000001* L0008272 00000011 00000011 00000000 00000011* L0008304 00000011 00000011 00000000 00000010* L0008336 00000010 00000011 00000001 00000000* L0008368 00000001 00000010 00000001 00000010* L0008400 00000011 00000011 00000001 00000010* -L0008432 00000000 00000011 00000000 00000000* +L0008432 00100000 00000011 00000000 00000000* L0008464 00000001 00000011 00000001 00000011* L0008496 000000 000000 000000 000000* L0008520 000000 000000 000000 000000* -L0008544 000000 000000 000000 001000* +L0008544 000000 000000 000000 000000* L0008568 000000 000000 000000 000000* L0008592 000000 000000 000000 000000* L0008616 000000 000000 000000 000000* L0008640 00000000 00000000 00000000 00000000* L0008672 00000000 00000010 00000000 00000000* -L0008704 00000000 00000000 00000000 00000000* +L0008704 00000000 00000000 00000000 01000000* L0008736 00000000 00000000 00000000 00000000* L0008768 00000000 00000000 00000000 00000000* L0008800 00000000 00000000 00000000 00000000* @@ -355,23 +355,23 @@ L0008896 00000000 00000000 00000000 00000000* L0008928 000000 000000 000000 000000* L0008952 000000 000000 000000 000000* L0008976 000000 000000 000000 000000* -L0009000 000000 000000 000000 000001* +L0009000 000000 000000 000000 100000* L0009024 000000 000000 000000 000000* L0009048 000000 000000 000000 000000* L0009072 00000000 00000010 00000000 00000000* -L0009104 00001000 00000000 00000000 00000000* +L0009104 00001000 00000000 00001000 00000000* L0009136 00000000 00000010 00000000 00000000* L0009168 00000000 00000000 00000000 00000000* L0009200 00000000 00000000 00000000 00000000* L0009232 00000000 00000000 00000000 00000000* L0009264 01000000 00000000 00000000 00000000* -L0009296 00000000 00000000 00000000 00000000* -L0009328 00000000 00000000 00001000 00000000* +L0009296 00000000 00000000 00000000 00010000* +L0009328 00000000 00000000 00000000 00000000* L0009360 000000 000000 000000 000000* L0009384 000000 000000 000000 000000* L0009408 000010 000000 000000 000000* L0009432 000000 000000 000000 000000* -L0009456 000000 000000 000000 000000* +L0009456 000000 000000 000000 000001* L0009480 000000 000000 000000 000000* L0009504 00000000 00000000 00000000 00000000* L0009536 00000000 00000010 00000000 00000010* @@ -405,7 +405,7 @@ L0010320 000000 000000 000000 000001* L0010344 000000 000000 000000 000000* L0010368 00000000 00000000 00000000 00000000* L0010400 00000000 00000010 00000000 00000000* -L0010432 00000000 00000000 00000000 01000000* +L0010432 00000000 00000000 00000000 00000000* L0010464 00000000 00000000 00000000 00000000* L0010496 00000000 00000000 00000000 00000000* L0010528 00000000 00000000 00000000 00000000* @@ -415,33 +415,33 @@ L0010624 00000000 00000000 00000000 00000000* L0010656 000000 000000 000000 000000* L0010680 000000 000000 000000 000000* L0010704 000000 000010 000000 000000* -L0010728 000000 000000 000000 100000* +L0010728 000000 000000 000000 000000* L0010752 000000 000000 000000 000000* L0010776 000000 000000 000000 000000* L0010800 00000000 00000000 00000000 00000000* -L0010832 00010000 00000000 00000000 00000000* +L0010832 00010000 00000000 00000000 10001000* L0010864 00000000 00000010 00000000 00000000* L0010896 00000000 00000000 00000000 00000000* L0010928 00000000 00000000 00000000 00000000* -L0010960 00000000 00000000 00000100 00000000* +L0010960 00000000 00000000 00000000 00000000* L0010992 00000000 00000000 00000000 00000000* -L0011024 00000000 00000000 00000000 00010000* +L0011024 00000000 00000000 00000000 00000000* L0011056 00000000 00000000 00001000 00000000* L0011088 000000 000000 000000 000000* L0011112 000000 000010 000000 000000* L0011136 000001 000000 000000 000000* L0011160 000000 000000 000000 000000* -L0011184 000000 000000 000000 000001* +L0011184 000000 000000 000000 000000* L0011208 000000 000000 000000 000000* -L0011232 00000011 00000011 00000001 00000011* +L0011232 00000011 00000011 00010001 00000011* L0011264 00000011 00000011 00000011 00000011* L0011296 01110011 00000011 00000001 00000011* L0011328 00001111 00000011 00000001 00000011* L0011360 00000011 00000011 00000011 00000011* -L0011392 00000011 00000011 00010001 10000011* +L0011392 00000011 00000011 00000001 10000011* L0011424 00000011 00000011 00000001 00000011* L0011456 11000011 00000011 00000011 00000011* -L0011488 00000011 00000011 00000001 00000011* +L0011488 00000011 00000011 00000011 00000011* L0011520 000000 000000 000000 000000* L0011544 000000 000000 000000 000000* L0011568 000000 000000 000000 000000* @@ -495,43 +495,43 @@ L0012912 000000 000000 000000 000000* L0012936 000000 000000 000000 000000* L0012960 00000000 00000000 00000000 00000000* L0012992 00000000 00000010 00000000 00000011* -L0013024 00000000 10000000 00000000 10111100* -L0013056 00000000 00000000 00000000 01000000* -L0013088 00000000 00000000 00000010 00000011* +L0013024 00000000 00000000 00000000 10111100* +L0013056 00000000 10000000 00000000 01000000* +L0013088 00000000 10000000 00000010 00000011* L0013120 00000000 00000000 00000000 00000000* -L0013152 00000000 10000000 00000000 00000000* -L0013184 00000000 10000000 00000001 00000111* +L0013152 00000000 00000000 00000000 00000000* +L0013184 00000000 00000000 00000001 00000111* L0013216 00000000 00000000 00000000 00010000* -L0013248 000000 100000 000000 000000* +L0013248 000000 000000 000000 000000* L0013272 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L0013704 000000 000000 000000 000000* L0013728 000000 000000 000000 000000* L0013752 000000 000000 000000 000000* -L0013776 000000 100000 000000 000000* -L0013800 000000 100000 000000 000000* +L0013776 000000 000000 000000 000000* +L0013800 000000 000000 000000 000000* L0013824 00000000 00000000 00000001 00000000* -L0013856 00000001 00000000 00000011 00000010* +L0013856 00000001 00000000 00000010 00000010* L0013888 00000000 00000000 00000000 00000000* -L0013920 00000000 00000000 00000000 00000000* +L0013920 00000000 00000000 00000001 00000000* L0013952 00000001 00000000 00000010 00000011* L0013984 00000010 00000001 00000000 00000000* L0014016 00000000 00000000 00000000 00000000* L0014048 00000011 00000000 00000011 00000010* -L0014080 00000010 00000000 00000000 00000000* +L0014080 00000010 00000000 00000010 00000000* L0014112 000000 000000 000000 000000* L0014136 000000 000000 000000 000000* L0014160 000000 000000 000000 000000* @@ -539,9 +539,9 @@ L0014184 000000 000000 000000 000000* L0014208 000000 000000 000000 000000* L0014232 000000 000000 000000 000000* L0014256 00000011 00000011 00000000 00000011* -L0014288 00000010 00000111 00000000 00000001* +L0014288 00000010 00000111 00000001 00000001* L0014320 00000011 00000011 00000001 00000011* -L0014352 00000011 00000011 00000001 00000011* +L0014352 00000011 00000011 00000000 00000011* L0014384 00000010 00000011 00000001 00000000* L0014416 00000001 00000010 00000001 10000011* L0014448 00111111 00000011 00000001 00000011* @@ -554,9 +554,9 @@ L0014616 000000 000000 000000 000000* L0014640 000000 000000 000000 000000* L0014664 000000 000000 000000 000000* L0014688 00000011 00000011 00000000 00000011* -L0014720 00000010 00000011 00000000 00000001* +L0014720 00000010 00000011 00000001 00000001* L0014752 00000011 00000011 00000001 01000011* -L0014784 00000011 00000011 00000001 00000011* +L0014784 00000011 00000011 00000000 00000011* L0014816 00000010 00000011 00000001 00000000* L0014848 00000001 00000010 00000001 00000011* L0014880 00000011 00000011 00000001 00000011* @@ -677,7 +677,7 @@ L0018144 00000000 00000000 00000000 00000000* L0018176 00000000 00000000 00000000 00000001* L0018208 00000000 00000000 00000000 00000000* L0018240 00000000 00000000 00000000 00000000* -L0018272 00000000 00000000 00000001 00000000* +L0018272 00000000 00000000 00000000 00000000* L0018304 00000000 00000000 00000000 00000000* L0018336 00000000 00000000 00000000 00000000* L0018368 00000000 00000000 00000000 00000000* @@ -704,14 +704,14 @@ L0018936 000000 000000 000000 000000* L0018960 000000 000000 000000 000000* L0018984 000000 000000 000000 000000* L0019008 00000000 00000000 00000000 00000000* -L0019040 00000001 00000010 00000010 00000011* +L0019040 00000001 00000010 00001010 00000011* L0019072 00000000 00000000 00000000 00000000* L0019104 00000000 00000000 00000000 00000000* L0019136 00000001 00000000 00000010 00000011* L0019168 00000010 00000000 00000100 11100000* L0019200 00000000 00000000 01000000 00000000* L0019232 00000011 00000000 00000011 00000011* -L0019264 00000010 00000000 00001000 00000000* +L0019264 00000010 00000000 00000000 00000000* L0019296 000000 000000 000000 000000* L0019320 000000 000000 000000 000000* L0019344 000000 000000 000000 000000* @@ -726,7 +726,7 @@ L0019568 00000011 00000011 00000011 00000011* L0019600 00000011 00000011 00000001 00000011* L0019632 00000011 00000011 00000001 00000011* L0019664 00000011 00000011 00000011 00000011* -L0019696 00000011 00000011 00000001 00000011* +L0019696 00000011 00000011 00000011 00000011* L0019728 000000 000000 000000 000000* L0019752 000000 000000 000000 000000* L0019776 000000 000000 000000 000000* @@ -734,7 +734,7 @@ L0019800 000000 000000 000000 000000* L0019824 000000 000000 000000 000000* L0019848 000000 000000 000000 000000* L0019872 00000011 00000011 00000000 00000011* -L0019904 00000011 00000011 00000010 00000001* +L0019904 00000011 00000011 00000011 00000001* L0019936 00000011 00000011 00000001 00000011* L0019968 00000011 00000011 00000001 00000011* L0020000 00000011 00000011 00000010 00000000* @@ -763,7 +763,7 @@ L0020640 000000 000000 000000 000000* L0020664 000000 000000 000000 000000* L0020688 000000 000000 000000 000000* L0020712 000000 000000 000000 000000* -L0020736 00000011 00000011 00000000 00000001* +L0020736 00000011 00000011 00001000 00000001* L0020768 00000010 00000011 00000000 00000001* L0020800 00001111 00000011 00000000 00000011* L0020832 01110011 00000011 00000000 00000011* @@ -783,12 +783,12 @@ L0021200 00000000 00000010 00000000 00000000* L0021232 00000000 00000010 00000000 00000000* L0021264 00000000 00000000 00000000 00000000* L0021296 00000000 00000000 00000000 00000000* -L0021328 00000000 00000000 00010000 00000000* +L0021328 00000000 00000000 00000000 00000000* L0021360 00000000 00000000 00000000 00000000* L0021392 00000001 00000000 00000000 00000000* L0021424 00000000 00000000 00000000 00000000* L0021456 000000 000000 000000 000000* -L0021480 000000 000000 000000 000000* +L0021480 000000 000000 001000 000000* L0021504 000000 001000 000000 000000* L0021528 000000 000000 000000 000000* L0021552 000000 000000 000000 000000* @@ -826,38 +826,38 @@ L0022440 000000 000000 000000 000000* L0022464 00000000 00000000 00000000 00000000* L0022496 10000000 00000000 00000000 00000011* L0022528 01110000 00000000 00000100 00000000* -L0022560 10001000 00000000 00000000 00000000* +L0022560 10000100 00000000 00000000 00000000* L0022592 00000000 00000010 00000000 00000011* -L0022624 00011000 00000000 00000000 00000000* +L0022624 00110000 00000000 00000000 00000000* L0022656 00000000 00000000 00000000 00000000* -L0022688 11101100 00000000 10100000 00000000* -L0022720 00000100 00000000 00100000 00000000* +L0022688 11101000 00000000 10000000 00000000* +L0022720 00000000 00000000 00100000 00000000* L0022752 000001 000000 000000 000000* -L0022776 000000 000000 000000 000000* +L0022776 001000 000000 000000 000000* L0022800 000000 000000 000000 000000* -L0022824 101000 000000 000000 000000* -L0022848 011100 000000 000000 000000* +L0022824 110000 000000 000000 000000* +L0022848 011011 000000 000000 000000* L0022872 000000 000000 000000 000000* L0022896 00000001 00000001 00000000 00000010* L0022928 00000011 00000001 00000010 00000010* L0022960 00000000 00000000 00000000 00000000* -L0022992 00000100 00000000 00000000 00000000* +L0022992 00001000 00000000 00000000 00000000* L0023024 00000011 00000010 00000010 00000000* -L0023056 00100100 00000000 10100000 00000000* +L0023056 00001100 00000000 10100000 00000000* L0023088 00000000 00000000 00000000 00000000* -L0023120 00000000 00000000 00000000 00000000* -L0023152 00000000 00000000 00000000 00000000* +L0023120 00000100 00000000 00100000 00000000* +L0023152 00000100 00000000 00000000 00000000* L0023184 000000 000000 000000 000000* -L0023208 011000 000000 000000 000000* +L0023208 010000 000000 000000 000000* L0023232 000000 010000 000000 000000* -L0023256 010000 000000 000000 000000* -L0023280 000011 000000 000000 000000* +L0023256 001000 000000 000000 000000* +L0023280 000100 000000 000000 000000* L0023304 000000 000000 000000 000000* L0023328 00000000 00000001 00000000 00000000* L0023360 00000000 00000001 00000000 00000010* L0023392 00000000 00000010 00000000 00000000* -L0023424 00000000 10000000 00000000 00000000* -L0023456 00000000 10000001 00000000 00000010* +L0023424 00000000 00000000 00000000 00000000* +L0023456 00000000 00000001 00000000 00000010* L0023488 00000000 00000000 00000000 00000000* L0023520 00000000 10000000 00000000 00000000* L0023552 00000000 00000000 00000000 00000000* @@ -866,13 +866,13 @@ L0023616 000000 100000 000000 000000* L0023640 000000 000000 000000 000000* L0023664 000000 000000 000000 000000* L0023688 000000 000000 000000 000000* -L0023712 000000 000000 000000 000000* -L0023736 000000 000000 000000 000000* +L0023712 000000 100000 000000 000000* +L0023736 000000 100000 000000 000000* L0023760 00000000 00000010 00000000 00000000* L0023792 00000000 00000010 00000000 10000010* L0023824 00000000 10000000 00000010 00000000* -L0023856 00000000 00000000 00000000 00001000* -L0023888 00000000 00000010 00000000 00000010* +L0023856 00000000 10000000 00000000 00001000* +L0023888 00000000 10000010 00000000 00000010* L0023920 00000000 00000000 00000000 00000000* L0023952 00000000 00000000 00000000 00000000* L0023984 00000000 10000000 00000000 00000000* @@ -881,8 +881,8 @@ L0024048 000000 000000 000000 000000* L0024072 000000 000000 000000 000000* L0024096 000000 000000 000000 000010* L0024120 000000 000000 000000 000000* -L0024144 000000 100000 000000 000000* -L0024168 000000 100000 000000 000000* +L0024144 000000 000000 000000 000000* +L0024168 000000 000000 000000 000000* L0024192 00000010 00000001 00000000 00000000* L0024224 00000010 00000001 00000000 00000010* L0024256 00000000 00000000 00000000 00000000* @@ -898,11 +898,11 @@ L0024528 000000 000000 000000 000000* L0024552 000000 000000 000000 000000* L0024576 000000 000000 000000 000000* L0024600 000000 000000 000000 000000* -L0024624 00000001 00000000 00000001 00000000* +L0024624 00000000 00000000 00000000 00000000* L0024656 00000010 00000000 00000000 00000001* L0024688 00000000 00000000 00000000 00000000* L0024720 00000000 00000000 00000000 00000000* -L0024752 00000011 00000000 00000001 00000001* +L0024752 00000010 00000000 00000000 00000001* L0024784 00000000 00000000 00000000 00100000* L0024816 00000000 00000000 00000000 00000000* L0024848 00000000 00000000 00000000 00000000* @@ -928,8 +928,8 @@ L0025392 000000 000000 000000 000000* L0025416 000000 000000 000000 100000* L0025440 000000 000000 000000 000000* L0025464 000000 000000 000000 000000* -L0025488 00000001 00000000 00000001 00000010* -L0025520 00000011 00000000 00000000 00000010* +L0025488 00000011 00000000 00000001 00000010* +L0025520 00000011 00000000 00000000 00000000* L0025552 00000000 00000000 00000000 00000000* L0025584 00000000 00000000 00000000 00000000* L0025616 00000011 00000010 00000001 00000010* @@ -959,7 +959,7 @@ L0026280 000000 100001 000000 000000* L0026304 000000 000000 000000 000000* L0026328 000000 000000 000000 000000* L0026352 00000001 00000000 00000000 00000010* -L0026384 00000001 00000000 00000001 00000000* +L0026384 00000000 00000000 00000001 00000000* L0026416 00000000 00000000 00000010 00000000* L0026448 00000000 00000000 00000000 00000000* L0026480 00000011 00000000 00000001 00000010* @@ -974,15 +974,15 @@ L0026712 000000 000000 000000 000000* L0026736 000000 000000 000000 000000* L0026760 000000 000000 000000 000000* L0026784 00000001 00000001 00000011 00000010* -L0026816 00000011 00000001 00000001 00000000* +L0026816 00000011 00000001 00000001 00000010* L0026848 00000000 00000000 00000000 00000000* L0026880 00000000 00000000 00000000 00000000* -L0026912 00000010 10000010 00000000 00000010* +L0026912 00000010 00000010 00000010 00000010* L0026944 00000000 00000000 00000000 00000000* L0026976 00000000 00000000 00000000 00000000* L0027008 00000000 00000000 00000000 00000000* L0027040 00000000 00000000 00000000 00000000* -L0027072 000000 000000 000000 000000* +L0027072 000000 100000 000000 000000* L0027096 000000 000000 000000 000000* L0027120 000000 000000 000000 000000* L0027144 000000 000000 000000 000000* @@ -1033,11 +1033,11 @@ L0028416 000000 000000 000000 000000* L0028440 000000 000000 000000 000000* L0028464 000000 000000 000000 000000* L0028488 000000 000000 000000 000000* -L0028512 00000001 00000001 00000000 00000000* +L0028512 00000000 00000001 00000001 00000000* L0028544 10000010 00000011 00000000 00000010* L0028576 00000000 00000000 00000000 00000000* L0028608 10000000 00000000 00000000 00000000* -L0028640 00000001 00000011 00000000 00000000* +L0028640 00000000 00000011 00000000 00000000* L0028672 00000000 00000000 00000000 00000000* L0028704 00000000 00000000 00000000 00000000* L0028736 00000000 00000000 00000000 00000000* @@ -1064,40 +1064,40 @@ L0029304 000000 000000 000000 000000* L0029328 000000 000000 000000 000000* L0029352 000000 000000 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00000000 00000001 00000001* L0031264 00000000 00000000 00000000 00000000* L0031296 00000000 00000000 00000000 00000000* L0031328 00000000 00000000 00000000 00000000* @@ -1138,11 +1138,11 @@ L0031440 000000 000000 000000 000000* L0031464 000000 000000 000000 000000* L0031488 000000 000000 000000 000000* L0031512 000000 000000 000000 000000* -L0031536 00000000 00000000 00000000 00000000* -L0031568 00000001 00000001 00000000 00000000* +L0031536 00000000 00000000 00000000 00000001* +L0031568 00000001 00000001 00000000 00000001* L0031600 00000000 00000000 00000000 00000000* L0031632 00000000 00000000 00000000 00000000* -L0031664 00000001 00000000 00000000 00000000* +L0031664 00000001 00000000 00000000 00000001* L0031696 00000000 00000000 00000000 00000000* L0031728 00000000 00000000 00000000 00000000* L0031760 00000000 00000000 00100000 00000000* @@ -1153,11 +1153,11 @@ L0031872 000000 000000 000000 000000* L0031896 000000 000000 000000 000000* L0031920 001000 000000 000000 000000* L0031944 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00000000 00000000 00000000 00000000* L0033392 00000000 00000000 00000000 00000000* L0033424 00000000 00000000 00000000 00000000* L0033456 00000000 00000000 00000000 00000000* -L0033488 00100000 00000000 10000000 00000000* +L0033488 00000000 00000000 10000000 00000000* L0033520 00000000 00000000 00000000 00000000* L0033552 000000 000000 000000 000000* L0033576 000000 000000 000000 000000* @@ -1213,12 +1213,12 @@ L0033600 000000 000000 000000 000000* L0033624 000000 000000 000000 000000* L0033648 000000 000000 000000 000000* L0033672 000000 000000 000000 000000* -L0033696 00000010 00000010 00001010 00000010* +L0033696 00000010 00000010 00000010 00000010* L0033728 00000000 00000010 00000000 00000000* L0033760 00000000 00000000 00000000 00000000* L0033792 00000000 00111000 00000000 00000000* L0033824 00000000 00000000 00000000 00000000* -L0033856 00000000 00000000 01000000 00000000* +L0033856 00000000 00000000 01010000 00000000* L0033888 00111110 00000010 10100010 00000010* L0033920 00000000 00000000 00000000 00000000* L0033952 00000000 00110000 00000000 00000000* @@ -1335,25 +1335,25 @@ L0037104 000000 000000 000000 000000* L0037128 000000 000000 000000 000000* L0037152 00000000 00000000 00000000 00000000* L0037184 00000000 00000000 00000000 00000000* -L0037216 10000000 00000000 00000000 00000000* +L0037216 00000000 00000000 00000000 00000000* L0037248 00000000 00000000 00000000 00000000* L0037280 00000000 00000000 00000000 00000000* L0037312 00000000 00000000 00000000 00000000* L0037344 00000000 00000000 00000000 00000000* L0037376 00000000 00000000 00000000 00000000* L0037408 00000000 00000000 00000000 00000000* -L0037440 000000 100000 000000 000000* +L0037440 000000 000000 000000 000000* L0037464 000000 000000 000000 000000* L0037488 000000 000000 000000 000000* L0037512 000000 000000 000000 000000* L0037536 000000 000000 000000 000000* -L0037560 000000 000000 000000 000000* +L0037560 000000 100000 000000 000000* L0037584 00000000 00000000 00000000 00000000* -L0037616 00000000 00000000 00000000 00000000* +L0037616 00000000 00000000 00001000 00000000* L0037648 00000000 00000000 00000000 00000000* L0037680 00000000 00000000 00000000 00000000* L0037712 00000000 00000000 00000000 00000000* -L0037744 00000000 00000000 00000000 00000000* +L0037744 00000000 00000000 00000100 00000000* L0037776 00000000 00000000 00000000 00000000* L0037808 00000000 00000000 00000000 00000000* L0037840 00000000 00000000 00000000 00000000* @@ -1439,7 +1439,7 @@ L0040104 000000 000000 000000 000000* L0040128 000000 000000 000000 000000* L0040152 000000 000000 000000 000000* L0040176 00000000 00000000 00000000 00000000* -L0040208 00000000 00000000 00001000 00000000* +L0040208 00000000 00000000 00000000 00000000* L0040240 00000000 00000000 00000000 00000000* L0040272 00000000 00000000 00000000 00000000* L0040304 00000000 00000000 00000000 00000000* @@ -1449,17 +1449,17 @@ L0040400 00000000 00000000 00000000 00000000* L0040432 00000000 00000000 00000000 00000000* L0040464 000000 000000 000000 000000* L0040488 000000 000000 000000 000000* -L0040512 000000 000000 000000 000000* +L0040512 000000 000000 000100 000000* L0040536 000000 000000 000000 000000* L0040560 000000 000000 000000 000000* L0040584 000000 000000 000000 000000* L0040608 00000000 00000000 00000000 00000000* L0040640 00000000 00000000 00000000 00000000* L0040672 00000000 00000000 00000000 00000000* -L0040704 00000000 10000000 00000000 00000000* +L0040704 00000000 00000000 00000000 00000000* L0040736 00000000 00000000 00000000 00000000* L0040768 00000000 00000000 00000000 00000000* -L0040800 00000000 00000000 00000000 00000000* +L0040800 00000000 10000000 00000000 00000000* L0040832 00000000 00000000 00000000 00000000* L0040864 00000000 00000000 00000000 00000000* L0040896 000000 000000 000000 000000* @@ -1469,7 +1469,7 @@ L0040968 000000 000000 000000 000000* L0040992 000000 000000 000000 000000* L0041016 000000 000000 000000 000000* L0041040 00000000 00000000 00000000 00000000* -L0041072 00000000 00000000 00000000 00000000* +L0041072 01000000 00000000 00000000 00000000* L0041104 00000000 00000000 00000000 00000000* L0041136 00000000 00000000 00000000 00000000* L0041168 00000000 00000000 00000000 00000000* @@ -1514,34 +1514,34 @@ L0042264 000000 000000 000000 000000* L0042288 000000 000001 000000 000000* L0042312 000000 000000 000000 000000* L0042336 00000000 00000000 00000000 00000000* -L0042368 00000000 00000000 00000000 00000000* -L0042400 00000000 00000000 00000000 00000000* -L0042432 00000000 00000000 00000000 00000000* +L0042368 10000000 00000000 00000000 00000000* +L0042400 01110000 00000000 00000100 00000000* +L0042432 10001000 00000000 00000000 00000000* L0042464 00000000 00000000 00000000 00000000* -L0042496 00000000 00000000 00000000 00000000* +L0042496 00011000 00000000 00000000 00000000* L0042528 00000000 00000000 00000000 00000000* -L0042560 00000000 00000000 00000000 00000000* -L0042592 00000000 00000000 00000000 00000000* -L0042624 000000 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00000000 00000000 00000000 00000000* L0044560 00000000 10000000 00000000 00000000* L0044592 00000000 10000000 00000000 00000000* L0044624 00000000 00000000 00000000 00000000* @@ -1663,5 +1663,5 @@ L0046560 000000 000000 000000 000000* L0046584 000000 000000 000000 000000* L0046608 000000 000000 000000 000000* L0046632 000000 000000 000000 000000* -CAA5B* -1DA9 +CAD1B* +1DB3 diff --git a/VHDL/AppleIISd.sym b/VHDL/AppleIISd.sym deleted file mode 100644 index 18eecf0..0000000 --- a/VHDL/AppleIISd.sym +++ /dev/null @@ -1,57 +0,0 @@ - - - BLOCK - 2017-10-8T19:42:44 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/VHDL/AppleIISd.vhd b/VHDL/AppleIISd.vhd index 35c37fa..e286153 100644 --- a/VHDL/AppleIISd.vhd +++ b/VHDL/AppleIISd.vhd @@ -1,295 +1,187 @@ ---------------------------------------------------------------------------------- --- Company: n/a --- Engineer: A. Fachat +-- Company: +-- Engineer: -- --- Create Date: 12:37:11 05/07/2011 --- Design Name: SPI65B --- Module Name: SPI6502B - Behavioral --- Project Name: CS/A NETUSB 2.0 --- Target Devices: CS/A NETUSB 2.0 +-- Create Date: 20:44:25 10/09/2017 +-- Design Name: +-- Module Name: IO - Behavioral +-- Project Name: +-- Target Devices: -- Tool versions: --- Description: An SPI interface for 6502-based computers (or compatible). --- modelled after the SPI65 interface by Daryl Rictor --- (see http://sbc.rictor.org/io/65spi.html ) --- This implementation here, however, is a complete reimplementation --- as the ABEL language of the original implementation is not supported --- by ISE anymore. --- Also I added the interrupt input handling, replacing four of the --- original SPI select outputs with four interrupt inputs --- Also folded out the single MISO input into one input for each of the --- four supported devices, reducing external parts count again by one. +-- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created --- Revision 0.02 - removed spiclk and replaced with clksrc and clkcnt_is_zero combination, --- to drive up SPI clock to half of input clock (and not one fourth only as before) --- unfortunately that costed one divisor bit to fit into the CPLD -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; entity AppleIISd is Port ( - data_in : in STD_LOGIC_VECTOR (7 downto 0); - data_out : out STD_LOGIC_VECTOR (7 downto 0); - is_read : in STD_LOGIC; - nreset : in STD_LOGIC; - addr : in STD_LOGIC_VECTOR (1 downto 0); - phi0 : in STD_LOGIC; - ndev_sel : in STD_LOGIC; - clk : in STD_LOGIC; - miso: in std_logic; - mosi : out STD_LOGIC; - sclk : out STD_LOGIC; - nsel : out STD_LOGIC; - wp : in STD_LOGIC; - card : in STD_LOGIC; - led : out STD_LOGIC + ADD_HIGH : in std_logic_vector(10 downto 8); + ADD_LOW : in std_logic_vector(1 downto 0); + B : out std_logic_vector(10 downto 8); + CARD : in std_logic; + DATA : inout std_logic_vector (7 downto 0); + CLK : in std_logic; + LED : out std_logic; + NDEV_SEL : in std_logic; + NG : out std_logic; + NIO_SEL : in std_logic; + NIO_STB : in std_logic; + NOE : out std_logic; + PHI0 : in std_logic; + NRESET : in std_logic; + RNW : in std_logic; + MISO : in std_logic; + MOSI : out std_logic; + NSEL : out std_logic; + SCLK : out std_logic; + WP : in std_logic + + -- synthesis translate_off + ; + data_dbg : out std_logic_vector (7 downto 0); + add_dbg : out std_logic_vector (1 downto 0) + -- synthesis translate_on + ); - - constant DIV_WIDTH : integer := 3; - end AppleIISd; architecture Behavioral of AppleIISd is - - -------------------------- - -- internal state - signal spidatain: std_logic_vector (7 downto 0); - signal spidataout: std_logic_vector (7 downto 0); - signal inited: std_logic; -- card initialized - - -- spi register flags - signal tc: std_logic; -- transmission complete; cleared on spi data read - signal bsy: std_logic; -- SPI busy - signal frx: std_logic; -- fast receive mode - signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock - - signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0); - signal slavesel: std_logic := '1'; -- slave select output (0=selected) - signal int_miso: std_logic; - -------------------------- - -- helper signals - -- shift engine - signal start_shifting: std_logic := '0'; -- shifting data - signal shifting2: std_logic := '0'; -- shifting data - signal shiftdone: std_logic; -- shifting data done - signal shiftcnt: std_logic_vector(3 downto 0); -- shift counter (5 bit) + signal data_in : std_logic_vector (7 downto 0); + signal data_out : std_logic_vector (7 downto 0); + signal addr_low_int : std_logic_vector (1 downto 0); + signal wp_int : std_logic; + signal card_int : std_logic; + signal miso_int : std_logic; - -- spi clock - signal clksrc: std_logic; -- clock source (phi2 or clk_7m) - -- TODO divcnt is not used at all?? - --signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter - signal shiftclk : std_logic; - -begin - --led <= not (inited); - led <= not (bsy or not slavesel); - bsy <= start_shifting or shifting2; - - process(start_shifting, shiftdone, shiftclk) - begin - if (rising_edge(shiftclk)) then - if (shiftdone = '1') then - shifting2 <= '0'; - else - shifting2 <= start_shifting; - end if; - end if; - end process; - - process(shiftcnt, nreset, shiftclk) - begin - if (nreset = '0') then - shiftdone <= '0'; - elsif (rising_edge(shiftclk)) then - if (shiftcnt = "1111") then - shiftdone <= '1'; - else - shiftdone <= '0'; - end if; - end if; - end process; - - process(nreset, shifting2, shiftcnt, shiftclk) - begin - if (nreset = '0') then - shiftcnt <= (others => '0'); - elsif (rising_edge(shiftclk)) then - if (shifting2 = '1') then - -- count phase - shiftcnt <= shiftcnt + 1; - else - shiftcnt <= (others => '0'); - end if; - end if; - end process; - - inproc: process(nreset, shifting2, shiftcnt, shiftclk, spidatain, miso) - begin - if (nreset = '0') then - spidatain <= (others => '0'); - elsif (rising_edge(shiftclk)) then - if (shifting2 = '1' and shiftcnt(0) = '1') then - -- shift in to input register - spidatain (7 downto 1) <= spidatain (6 downto 0); - spidatain (0) <= int_miso; - end if; - end if; - end process; - - outproc: process(nreset, shifting2, spidataout, shiftcnt, shiftclk) - begin - if (nreset = '0') then - mosi <= '1'; - sclk <= '0'; - else - -- clock is sync'd - if (rising_edge(shiftclk)) then - if (shifting2='0' or shiftdone = '1') then - mosi <= '1'; - sclk <= '0'; - else - -- output data directly from output register - case shiftcnt(3 downto 1) is - when "000" => mosi <= spidataout(7); - when "001" => mosi <= spidataout(6); - when "010" => mosi <= spidataout(5); - when "011" => mosi <= spidataout(4); - when "100" => mosi <= spidataout(3); - when "101" => mosi <= spidataout(2); - when "110" => mosi <= spidataout(1); - when "111" => mosi <= spidataout(0); - when others => mosi <= '1'; - end case; - sclk <= '0' xor '0' xor shiftcnt(0); - end if; - end if; - end if; - end process; - - - -- shift operation enable - shiften: process(nreset, ndev_sel, is_read, addr, frx, shiftdone) - begin - -- start shifting - if (nreset = '0' or shiftdone = '1') then - start_shifting <= '0'; - elsif (rising_edge(ndev_sel) and addr="00" and (frx='1' or is_read='0')) then - -- access to register 00, either write (is_read=0) or fast receive bit set (frx) - -- then both types of access (write but also read) - start_shifting <= '1'; - end if; - end process; - - -------------------------- - -- spiclk - spi clock generation - -- spiclk is still 2 times the freq. than sclk - clksrc <= phi0 when (ece = '0') else clk; - - -- is a pulse signal to allow for divisor==0 - --shiftclk <= clksrc when divcnt = "000000" else '0'; - shiftclk <= clksrc when bsy = '1' else '0'; - --- clkgen: process(nreset, divisor, clksrc) --- begin --- if (nreset = '0') then --- divcnt <= divisor; --- elsif (falling_edge(clksrc)) then --- if (shiftclk = '1') then --- divcnt <= divisor; --- else --- divcnt <= divcnt - 1; --- end if; --- end if; --- end process; - - -------------------------- - -- interface section - -- inputs - int_miso <= (miso and not slavesel); + signal ndev_sel_int : std_logic; + signal rnw_int : std_logic; + signal data_en : std_logic; - -- outputs - nsel <= slavesel; +component SpiController is +Port ( + data_in : in std_logic_vector (7 downto 0); + data_out : out std_logic_vector (7 downto 0); + is_read : in std_logic; + nreset : in std_logic; + addr : in std_logic_vector (1 downto 0); + phi0 : in std_logic; + ndev_sel : in std_logic; + clk : in std_logic; + miso: in std_logic; + mosi : out std_logic; + sclk : out std_logic; + nsel : out std_logic; + wp : in std_logic; + card : in std_logic; + led : out std_logic + ); +end component; - tc_proc: process (ndev_sel, shiftdone) +component AddressDecoder +Port ( + A : in std_logic_vector (10 downto 8); + B : out std_logic_vector (10 downto 8); + RNW : in std_logic; + NDEV_SEL : in std_logic; + NIO_SEL : in std_logic; + NIO_STB : in std_logic; + NRESET : in std_logic; + DATA_EN : out std_logic; + NG : out std_logic; + NOE : out std_logic + ); +end component; + +begin + spi: SpiController port map( + data_in => data_in, + data_out => data_out, + is_read => rnw_int, + nreset => NRESET, + addr => addr_low_int, + phi0 => PHI0, + ndev_sel => ndev_sel_int, + clk => CLK, + miso => miso_int, + mosi => MOSI, + sclk => SCLK, + nsel => NSEL, + wp => wp_int, + card => card_int, + led => LED + ); + + addDec: AddressDecoder port map( + A => ADD_HIGH, + B => B, + RNW => RNW, + NDEV_SEL => NDEV_SEL, + NIO_SEL => NIO_SEL, + NIO_STB => NIO_STB, + NRESET => NRESET, + DATA_EN => data_en, + NOE => NOE, + NG => NG + ); + + ctrl_latch: process(CLK, NRESET) begin - if (shiftdone = '1') then - tc <= '1'; - elsif (rising_edge(ndev_sel) and addr="00") then - tc <= '0'; + if(NRESET = '0') then + ndev_sel_int <= '1'; + rnw_int <= '1'; + wp_int <= '1'; + card_int <= '1'; + miso_int <= '1'; + elsif rising_edge(CLK) then + ndev_sel_int <= NDEV_SEL; + rnw_int <= RNW; + wp_int <= WP; + card_int <= CARD; + miso_int <= MISO; end if; end process; - -------------------------- - -- cpu register section - -- cpu read - cpu_read: process(addr, spidatain, tc, bsy, frx, - ece, divisor, slavesel, wp, card, inited) + DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate + + -- synthesis translate_off + --data_dbg <= data_in; + --add_dbg <= addr_low_int; + -- synthesis translate_on + + data_latch: process(CLK) begin - case addr is - when "00" => -- read SPI data in - data_out <= spidatain; - when "01" => -- read status register - data_out(0) <= '0'; - data_out(1) <= '0'; - data_out(2) <= ece; - data_out(3) <= '0'; - data_out(4) <= frx; - data_out(5) <= bsy; - data_out(6) <= '0'; - data_out(7) <= tc; - when "10" => -- read sclk divisor - data_out(DIV_WIDTH-1 downto 0) <= divisor; - data_out(7 downto 3) <= (others => '0'); - when "11" => -- read slave select / slave interrupt state - data_out(0) <= slavesel; - data_out(4 downto 1) <= (others => '0'); - data_out(5) <= wp; - data_out(6) <= card; - data_out(7) <= inited; - when others => - data_out <= (others => '0'); - end case; - end process; - - -- cpu write - cpu_write: process(nreset, ndev_sel, is_read, addr, data_in, card, inited) - begin - if (nreset = '0') then - ece <= '0'; - frx <= '0'; - slavesel <= '1'; - divisor <= (others => '0'); - spidataout <= (others => '1'); - inited <= '0'; - elsif (card = '1') then - inited <= '0'; - elsif (rising_edge(ndev_sel) and is_read = '0') then - case addr is - when "00" => -- write SPI data out (see other process above) - spidataout <= data_in; - when "01" => -- write status register - ece <= data_in(2); - frx <= data_in(4); - -- no bit 5 - 7 - when "10" => -- write divisor - divisor <= data_in(DIV_WIDTH-1 downto 0); - when "11" => -- write slave select / slave interrupt enable - slavesel <= data_in(0); - -- no bit 1 - 6 - inited <= data_in(7); - when others => - end case; + --if(rising_edge(CLK) and NDEV_SEL = '0') and (RNW = '0')) then + --if rising_edge(CLK) and (NDEV_SEL = '0') then + if rising_edge(CLK) then + if (NDEV_SEL = '0') then + data_in <= DATA; + end if; end if; end process; + add_latch: process(NDEV_SEL) + begin + if falling_edge(NDEV_SEL) then + addr_low_int <= ADD_LOW; + end if; + end process; + end Behavioral; diff --git a/VHDL/AppleIISd.xise b/VHDL/AppleIISd.xise index 73b666e..76c5301 100644 --- a/VHDL/AppleIISd.xise +++ b/VHDL/AppleIISd.xise @@ -15,23 +15,23 @@ - + - + - - + + - + @@ -84,9 +84,9 @@ - - - + + + @@ -124,14 +124,14 @@ - + - + @@ -140,7 +140,7 @@ - + @@ -148,8 +148,8 @@ - - + + @@ -159,7 +159,7 @@ - + @@ -194,7 +194,7 @@ - + diff --git a/VHDL/AppleIISd_Test.vhd b/VHDL/AppleIISd_Test.vhd index 1866a58..b5ea6ef 100644 --- a/VHDL/AppleIISd_Test.vhd +++ b/VHDL/AppleIISd_Test.vhd @@ -2,15 +2,15 @@ -- Company: -- Engineer: -- --- Create Date: 20:21:20 10/09/2017 +-- Create Date: 00:42:59 10/10/2017 -- Design Name: --- Module Name: U:/AppleIISd/VHDL/AppleIISd_Test.vhd +-- Module Name: U:/AppleIISd/VHDL/IO_Test.vhd -- Project Name: AppleIISd -- Target Device: -- Tool versions: -- Description: -- --- VHDL Test Bench Created by ISE for module: AppleIISd +-- VHDL Test Bench Created by ISE for module: IO -- -- Dependencies: -- @@ -41,107 +41,184 @@ ARCHITECTURE behavior OF AppleIISd_Test IS COMPONENT AppleIISd PORT( - data_in : IN std_logic_vector(7 downto 0); - data_out : OUT std_logic_vector(7 downto 0); - is_read : IN std_logic; - reset : IN std_logic; - addr : IN std_logic_vector(1 downto 0); - phi0 : IN std_logic; - selected : IN std_logic; - clk : IN std_logic; - miso : IN std_logic; - mosi : OUT std_logic; - sclk : OUT std_logic; - nsel : OUT std_logic; - wp : IN std_logic; - card : IN std_logic; - led : OUT std_logic + ADD_HIGH : IN std_logic_vector(10 downto 8); + ADD_LOW : IN std_logic_vector(1 downto 0); + B : OUT std_logic_vector(10 downto 8); + CARD : IN std_logic; + DATA : INOUT std_logic_vector(7 downto 0); + CLK : IN std_logic; + LED : OUT std_logic; + NDEV_SEL : IN std_logic; + NG : OUT std_logic; + NIO_SEL : IN std_logic; + NIO_STB : IN std_logic; + NOE : OUT std_logic; + PHI0 : IN std_logic; + NRESET : IN std_logic; + RNW : IN std_logic; + MISO : IN std_logic; + MOSI : OUT std_logic; + NSEL : OUT std_logic; + SCLK : OUT std_logic; + WP : IN std_logic; + + data_dbg : out std_logic_vector (7 downto 0); + add_dbg : out std_logic_vector (1 downto 0) ); END COMPONENT; --Inputs - signal data_in : std_logic_vector(7 downto 0) := (others => '1'); - signal is_read : std_logic := '0'; - signal reset : std_logic := '0'; - signal addr : std_logic_vector(1 downto 0) := (others => '0'); - signal phi0 : std_logic := '1'; - signal selected : std_logic := '0'; - signal clk : std_logic := '0'; - signal miso : std_logic := '0'; - signal wp : std_logic := '0'; - signal card : std_logic := '0'; + signal ADD_HIGH : std_logic_vector(10 downto 8) := (others => 'U'); + signal ADD_LOW : std_logic_vector(1 downto 0) := (others => 'U'); + signal CARD : std_logic := '0'; + signal CLK : std_logic := '0'; + signal NDEV_SEL : std_logic := '1'; + signal NIO_SEL : std_logic := '1'; + signal NIO_STB : std_logic := '1'; + signal PHI0 : std_logic := '0'; + signal NRESET : std_logic := '1'; + signal RNW : std_logic := '1'; + signal MISO : std_logic := '1'; + signal WP : std_logic := '0'; + + --BiDirs + signal DATA : std_logic_vector(7 downto 0) := (others => 'Z'); --Outputs - signal data_out : std_logic_vector(7 downto 0); - signal mosi : std_logic; - signal sclk : std_logic; - signal nsel : std_logic; - signal led : std_logic; + signal B : std_logic_vector(10 downto 8); + signal LED : std_logic; + signal NG : std_logic; + signal NOE : std_logic; + signal MOSI : std_logic; + signal NSEL : std_logic; + signal SCLK : std_logic; + + signal data_dbg : std_logic_vector (7 downto 0); + signal add_dbg : std_logic_vector (1 downto 0); -- Clock period definitions - constant clk_period : time := 142 ns; -- 7MHz + constant CLK_period : time := 142 ns; + + -- Bus timings + -- worst case + constant ADD_valid : time := 300 ns; -- II+ + constant DATA_valid : time := 200 ns; -- II+ + constant ADD_hold : time := 15 ns; -- IIgs + --best case + --constant ADD_valid : time := 100 ns; -- IIgs + --constant DATA_valid : time := 30 ns; -- IIgs + --constant ADD_hold : time := 15 ns; -- IIgs BEGIN -- Instantiate the Unit Under Test (UUT) uut: AppleIISd PORT MAP ( - data_in => data_in, - data_out => data_out, - is_read => is_read, - reset => reset, - addr => addr, - phi0 => phi0, - selected => selected, - clk => clk, - miso => miso, - mosi => mosi, - sclk => sclk, - nsel => nsel, - wp => wp, - card => card, - led => led + ADD_HIGH => ADD_HIGH, + ADD_LOW => ADD_LOW, + B => B, + CARD => CARD, + DATA => DATA, + CLK => CLK, + LED => LED, + NDEV_SEL => NDEV_SEL, + NG => NG, + NIO_SEL => NIO_SEL, + NIO_STB => NIO_STB, + NOE => NOE, + PHI0 => PHI0, + NRESET => NRESET, + RNW => RNW, + MISO => MISO, + MOSI => MOSI, + NSEL => NSEL, + SCLK => SCLK, + WP => WP, + + data_dbg => data_dbg, + add_dbg => add_dbg ); -- Clock process definitions - clk_process :process + CLK_process :process begin - clk <= '0'; - wait for clk_period/2; - clk <= '1'; - wait for clk_period/2; - end process; - - phi0_process :process(clk) + CLK <= '0'; + wait for CLK_period/2; + CLK <= '1'; + wait for CLK_period/2; + end process; + + PHI0_process :process(CLK) variable counter : integer range 0 to 7; begin - if rising_edge(clk) or falling_edge(clk) then + if rising_edge(CLK) or falling_edge(CLK) then counter := counter + 1; if counter = 7 then - phi0 <= not phi0; + PHI0 <= not PHI0; counter := 0; end if; end if; end process; + -- Stimulus process stim_proc: process begin -- hold reset state. - wait for clk_period * 20; - reset <= '1'; - wait for clk_period * 20; - reset <= '0'; - wait for clk_period * 5; - wait until rising_edge(phi0); - -- insert stimulus here - selected <= '1'; - wait for clk_period; - data_in <= (others => '0'); - wait until falling_edge(phi0); - selected <= '0'; - wait for clk_period; - data_in <= (others => '1'); + wait for CLK_period * 20; + NRESET <= '0'; + wait for CLK_period * 20; + NRESET <= '1'; + wait for CLK_period * 10; + + -- read reg 0 + DATA <= (others => 'Z'); + ADD_LOW <= (others => 'U'); + wait until falling_edge(PHI0); + wait for ADD_valid; + ADD_LOW <= (others => '0'); + RNW <= '1'; + DATA <= (others => 'U'); + wait until rising_edge(PHI0); + NDEV_SEL <= '0'; + DATA <= (others => 'Z'); + wait until falling_edge(PHI0); + NDEV_SEL <= '1'; + wait for ADD_hold; + ADD_LOW <= (others => 'U'); + + -- read reg 3 + wait until falling_edge(PHI0); + wait for ADD_valid; + ADD_LOW <= (others => '1'); + RNW <= '1'; + DATA <= (others => 'U'); + wait until rising_edge(PHI0); + NDEV_SEL <= '0'; + DATA <= (others => 'Z'); + wait until falling_edge(PHI0); + NDEV_SEL <= '1'; + wait for ADD_hold; + ADD_LOW <= (others => 'U'); + + -- send data + wait until falling_edge(PHI0); + wait for ADD_valid; + ADD_LOW <= (others => '0'); + RNW <= '0'; + DATA <= (others => 'U'); + wait until rising_edge(PHI0); + NDEV_SEL <= '0'; + DATA <= (others => 'Z'); + wait for DATA_valid; + DATA <= (others => '0'); + wait until falling_edge(PHI0); + NDEV_SEL <= '1'; + wait for ADD_hold; + wait for CLK_period; + ADD_LOW <= (others => 'U'); + RNW <= '1'; + DATA <= (others => 'Z'); wait; end process; diff --git a/VHDL/IO.vhd b/VHDL/IO.vhd deleted file mode 100644 index 30e87fa..0000000 --- a/VHDL/IO.vhd +++ /dev/null @@ -1,187 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 20:44:25 10/09/2017 --- Design Name: --- Module Name: IO - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity IO is -Port ( - ADD_HIGH : in std_logic_vector(10 downto 8); - ADD_LOW : in std_logic_vector(1 downto 0); - B : out std_logic_vector(10 downto 8); - CARD : in std_logic; - DATA : inout std_logic_vector (7 downto 0); - CLK : in std_logic; - LED : out std_logic; - NDEV_SEL : in std_logic; - NG : out std_logic; - NIO_SEL : in std_logic; - NIO_STB : in std_logic; - NOE : out std_logic; - PHI0 : in std_logic; - NRESET : in std_logic; - RNW : in std_logic; - MISO : in std_logic; - MOSI : out std_logic; - NSEL : out std_logic; - SCLK : out std_logic; - WP : in std_logic - - -- synthesis translate_off - ; - data_dbg : out std_logic_vector (7 downto 0); - add_dbg : out std_logic_vector (1 downto 0) - -- synthesis translate_on - - ); -end IO; - -architecture Behavioral of IO is - - signal data_in : std_logic_vector (7 downto 0); - signal data_out : std_logic_vector (7 downto 0); - signal addr_low_int : std_logic_vector (1 downto 0); - signal wp_int : std_logic; - signal card_int : std_logic; - signal miso_int : std_logic; - - signal ndev_sel_int : std_logic; - signal rnw_int : std_logic; - signal data_en : std_logic; - -component AppleIISd is -Port ( - data_in : in std_logic_vector (7 downto 0); - data_out : out std_logic_vector (7 downto 0); - is_read : in std_logic; - nreset : in std_logic; - addr : in std_logic_vector (1 downto 0); - phi0 : in std_logic; - ndev_sel : in std_logic; - clk : in std_logic; - miso: in std_logic; - mosi : out std_logic; - sclk : out std_logic; - nsel : out std_logic; - wp : in std_logic; - card : in std_logic; - led : out std_logic - ); -end component; - -component AddressDecoder -Port ( - A : in std_logic_vector (10 downto 8); - B : out std_logic_vector (10 downto 8); - RNW : in std_logic; - NDEV_SEL : in std_logic; - NIO_SEL : in std_logic; - NIO_STB : in std_logic; - NRESET : in std_logic; - DATA_EN : out std_logic; - NG : out std_logic; - NOE : out std_logic - ); -end component; - -begin - spi: AppleIISd port map( - data_in => data_in, - data_out => data_out, - is_read => rnw_int, - nreset => NRESET, - addr => addr_low_int, - phi0 => PHI0, - ndev_sel => ndev_sel_int, - clk => CLK, - miso => miso_int, - mosi => MOSI, - sclk => SCLK, - nsel => NSEL, - wp => wp_int, - card => card_int, - led => LED - ); - - addDec: AddressDecoder port map( - A => ADD_HIGH, - B => B, - RNW => RNW, - NDEV_SEL => NDEV_SEL, - NIO_SEL => NIO_SEL, - NIO_STB => NIO_STB, - NRESET => NRESET, - DATA_EN => data_en, - NOE => NOE, - NG => NG - ); - - ctrl_latch: process(CLK, NRESET) - begin - if(NRESET = '0') then - ndev_sel_int <= '1'; - rnw_int <= '1'; - wp_int <= '1'; - card_int <= '1'; - miso_int <= '1'; - elsif rising_edge(CLK) then - ndev_sel_int <= NDEV_SEL; - rnw_int <= RNW; - wp_int <= WP; - card_int <= CARD; - miso_int <= MISO; - end if; - end process; - - DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate - - -- synthesis translate_off - --data_dbg <= data_in; - --add_dbg <= addr_low_int; - -- synthesis translate_on - - data_latch: process(CLK) - begin - --if(rising_edge(CLK) and NDEV_SEL = '0') and (RNW = '0')) then - --if rising_edge(CLK) and (NDEV_SEL = '0') then - if rising_edge(CLK) then - if (NDEV_SEL = '0') then - data_in <= DATA; - end if; - end if; - end process; - - add_latch: process(NDEV_SEL) - begin - if falling_edge(NDEV_SEL) then - addr_low_int <= ADD_LOW; - end if; - end process; - -end Behavioral; - diff --git a/VHDL/IO_Test.vhd b/VHDL/IO_Test.vhd deleted file mode 100644 index 8657f51..0000000 --- a/VHDL/IO_Test.vhd +++ /dev/null @@ -1,225 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 00:42:59 10/10/2017 --- Design Name: --- Module Name: U:/AppleIISd/VHDL/IO_Test.vhd --- Project Name: AppleIISd --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: IO --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---USE ieee.numeric_std.ALL; - -ENTITY IO_Test IS -END IO_Test; - -ARCHITECTURE behavior OF IO_Test IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT IO - PORT( - ADD_HIGH : IN std_logic_vector(10 downto 8); - ADD_LOW : IN std_logic_vector(1 downto 0); - B : OUT std_logic_vector(10 downto 8); - CARD : IN std_logic; - DATA : INOUT std_logic_vector(7 downto 0); - CLK : IN std_logic; - LED : OUT std_logic; - NDEV_SEL : IN std_logic; - NG : OUT std_logic; - NIO_SEL : IN std_logic; - NIO_STB : IN std_logic; - NOE : OUT std_logic; - PHI0 : IN std_logic; - NRESET : IN std_logic; - RNW : IN std_logic; - MISO : IN std_logic; - MOSI : OUT std_logic; - NSEL : OUT std_logic; - SCLK : OUT std_logic; - WP : IN std_logic; - - data_dbg : out std_logic_vector (7 downto 0); - add_dbg : out std_logic_vector (1 downto 0) - ); - END COMPONENT; - - - --Inputs - signal ADD_HIGH : std_logic_vector(10 downto 8) := (others => 'U'); - signal ADD_LOW : std_logic_vector(1 downto 0) := (others => 'U'); - signal CARD : std_logic := '0'; - signal CLK : std_logic := '0'; - signal NDEV_SEL : std_logic := '1'; - signal NIO_SEL : std_logic := '1'; - signal NIO_STB : std_logic := '1'; - signal PHI0 : std_logic := '0'; - signal NRESET : std_logic := '1'; - signal RNW : std_logic := '1'; - signal MISO : std_logic := '1'; - signal WP : std_logic := '0'; - - --BiDirs - signal DATA : std_logic_vector(7 downto 0) := (others => 'Z'); - - --Outputs - signal B : std_logic_vector(10 downto 8); - signal LED : std_logic; - signal NG : std_logic; - signal NOE : std_logic; - signal MOSI : std_logic; - signal NSEL : std_logic; - signal SCLK : std_logic; - - signal data_dbg : std_logic_vector (7 downto 0); - signal add_dbg : std_logic_vector (1 downto 0); - - -- Clock period definitions - constant CLK_period : time := 142 ns; - - -- Bus timings - -- worst case - constant ADD_valid : time := 300 ns; -- II+ - constant DATA_valid : time := 200 ns; -- II+ - constant ADD_hold : time := 15 ns; -- IIgs - --best case - --constant ADD_valid : time := 100 ns; -- IIgs - --constant DATA_valid : time := 30 ns; -- IIgs - --constant ADD_hold : time := 15 ns; -- IIgs - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: IO PORT MAP ( - ADD_HIGH => ADD_HIGH, - ADD_LOW => ADD_LOW, - B => B, - CARD => CARD, - DATA => DATA, - CLK => CLK, - LED => LED, - NDEV_SEL => NDEV_SEL, - NG => NG, - NIO_SEL => NIO_SEL, - NIO_STB => NIO_STB, - NOE => NOE, - PHI0 => PHI0, - NRESET => NRESET, - RNW => RNW, - MISO => MISO, - MOSI => MOSI, - NSEL => NSEL, - SCLK => SCLK, - WP => WP, - - data_dbg => data_dbg, - add_dbg => add_dbg - ); - - -- Clock process definitions - CLK_process :process - begin - CLK <= '0'; - wait for CLK_period/2; - CLK <= '1'; - wait for CLK_period/2; - end process; - - PHI0_process :process(CLK) - variable counter : integer range 0 to 7; - begin - if rising_edge(CLK) or falling_edge(CLK) then - counter := counter + 1; - if counter = 7 then - PHI0 <= not PHI0; - counter := 0; - end if; - end if; - end process; - - - -- Stimulus process - stim_proc: process - begin - -- hold reset state. - wait for CLK_period * 20; - NRESET <= '0'; - wait for CLK_period * 20; - NRESET <= '1'; - wait for CLK_period * 10; - - -- read reg 0 - DATA <= (others => 'Z'); - ADD_LOW <= (others => 'U'); - wait until falling_edge(PHI0); - wait for ADD_valid; - ADD_LOW <= (others => '0'); - RNW <= '1'; - DATA <= (others => 'U'); - wait until rising_edge(PHI0); - NDEV_SEL <= '0'; - DATA <= (others => 'Z'); - wait until falling_edge(PHI0); - NDEV_SEL <= '1'; - wait for ADD_hold; - ADD_LOW <= (others => 'U'); - - -- read reg 3 - wait until falling_edge(PHI0); - wait for ADD_valid; - ADD_LOW <= (others => '1'); - RNW <= '1'; - DATA <= (others => 'U'); - wait until rising_edge(PHI0); - NDEV_SEL <= '0'; - DATA <= (others => 'Z'); - wait until falling_edge(PHI0); - NDEV_SEL <= '1'; - wait for ADD_hold; - ADD_LOW <= (others => 'U'); - - -- send data - wait until falling_edge(PHI0); - wait for ADD_valid; - ADD_LOW <= (others => '0'); - RNW <= '0'; - DATA <= (others => 'U'); - wait until rising_edge(PHI0); - NDEV_SEL <= '0'; - DATA <= (others => 'Z'); - wait for DATA_valid; - DATA <= (others => '0'); - wait until falling_edge(PHI0); - NDEV_SEL <= '1'; - wait for ADD_hold; - --wait for CLK_period; - ADD_LOW <= (others => 'U'); - RNW <= '1'; - DATA <= (others => 'Z'); - wait; - end process; - -END; diff --git a/VHDL/SpiController.vhd b/VHDL/SpiController.vhd new file mode 100644 index 0000000..b4f3e14 --- /dev/null +++ b/VHDL/SpiController.vhd @@ -0,0 +1,295 @@ +---------------------------------------------------------------------------------- +-- Company: n/a +-- Engineer: A. Fachat +-- +-- Create Date: 12:37:11 05/07/2011 +-- Design Name: SPI65B +-- Module Name: SPI6502B - Behavioral +-- Project Name: CS/A NETUSB 2.0 +-- Target Devices: CS/A NETUSB 2.0 +-- Tool versions: +-- Description: An SPI interface for 6502-based computers (or compatible). +-- modelled after the SPI65 interface by Daryl Rictor +-- (see http://sbc.rictor.org/io/65spi.html ) +-- This implementation here, however, is a complete reimplementation +-- as the ABEL language of the original implementation is not supported +-- by ISE anymore. +-- Also I added the interrupt input handling, replacing four of the +-- original SPI select outputs with four interrupt inputs +-- Also folded out the single MISO input into one input for each of the +-- four supported devices, reducing external parts count again by one. +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Revision 0.02 - removed spiclk and replaced with clksrc and clkcnt_is_zero combination, +-- to drive up SPI clock to half of input clock (and not one fourth only as before) +-- unfortunately that costed one divisor bit to fit into the CPLD +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +entity SpiController is +Port ( + data_in : in STD_LOGIC_VECTOR (7 downto 0); + data_out : out STD_LOGIC_VECTOR (7 downto 0); + is_read : in STD_LOGIC; + nreset : in STD_LOGIC; + addr : in STD_LOGIC_VECTOR (1 downto 0); + phi0 : in STD_LOGIC; + ndev_sel : in STD_LOGIC; + clk : in STD_LOGIC; + miso: in std_logic; + mosi : out STD_LOGIC; + sclk : out STD_LOGIC; + nsel : out STD_LOGIC; + wp : in STD_LOGIC; + card : in STD_LOGIC; + led : out STD_LOGIC + ); + + constant DIV_WIDTH : integer := 3; + +end SpiController; + +architecture Behavioral of SpiController is + + -------------------------- + -- internal state + signal spidatain: std_logic_vector (7 downto 0); + signal spidataout: std_logic_vector (7 downto 0); + signal inited: std_logic; -- card initialized + + -- spi register flags + signal tc: std_logic; -- transmission complete; cleared on spi data read + signal bsy: std_logic; -- SPI busy + signal frx: std_logic; -- fast receive mode + signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock + + signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0); + signal slavesel: std_logic := '1'; -- slave select output (0=selected) + signal int_miso: std_logic; + -------------------------- + -- helper signals + + -- shift engine + signal start_shifting: std_logic := '0'; -- shifting data + signal shifting2: std_logic := '0'; -- shifting data + signal shiftdone: std_logic; -- shifting data done + signal shiftcnt: std_logic_vector(3 downto 0); -- shift counter (5 bit) + + -- spi clock + signal clksrc: std_logic; -- clock source (phi2 or clk_7m) + -- TODO divcnt is not used at all?? + --signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter + signal shiftclk : std_logic; + +begin + --led <= not (inited); + led <= not (bsy or not slavesel); + bsy <= start_shifting or shifting2; + + process(start_shifting, shiftdone, shiftclk) + begin + if (rising_edge(shiftclk)) then + if (shiftdone = '1') then + shifting2 <= '0'; + else + shifting2 <= start_shifting; + end if; + end if; + end process; + + process(shiftcnt, nreset, shiftclk) + begin + if (nreset = '0') then + shiftdone <= '0'; + elsif (rising_edge(shiftclk)) then + if (shiftcnt = "1111") then + shiftdone <= '1'; + else + shiftdone <= '0'; + end if; + end if; + end process; + + process(nreset, shifting2, shiftcnt, shiftclk) + begin + if (nreset = '0') then + shiftcnt <= (others => '0'); + elsif (rising_edge(shiftclk)) then + if (shifting2 = '1') then + -- count phase + shiftcnt <= shiftcnt + 1; + else + shiftcnt <= (others => '0'); + end if; + end if; + end process; + + inproc: process(nreset, shifting2, shiftcnt, shiftclk, spidatain, miso) + begin + if (nreset = '0') then + spidatain <= (others => '0'); + elsif (rising_edge(shiftclk)) then + if (shifting2 = '1' and shiftcnt(0) = '1') then + -- shift in to input register + spidatain (7 downto 1) <= spidatain (6 downto 0); + spidatain (0) <= int_miso; + end if; + end if; + end process; + + outproc: process(nreset, shifting2, spidataout, shiftcnt, shiftclk) + begin + if (nreset = '0') then + mosi <= '1'; + sclk <= '0'; + else + -- clock is sync'd + if (rising_edge(shiftclk)) then + if (shifting2='0' or shiftdone = '1') then + mosi <= '1'; + sclk <= '0'; + else + -- output data directly from output register + case shiftcnt(3 downto 1) is + when "000" => mosi <= spidataout(7); + when "001" => mosi <= spidataout(6); + when "010" => mosi <= spidataout(5); + when "011" => mosi <= spidataout(4); + when "100" => mosi <= spidataout(3); + when "101" => mosi <= spidataout(2); + when "110" => mosi <= spidataout(1); + when "111" => mosi <= spidataout(0); + when others => mosi <= '1'; + end case; + sclk <= '0' xor '0' xor shiftcnt(0); + end if; + end if; + end if; + end process; + + + -- shift operation enable + shiften: process(nreset, ndev_sel, is_read, addr, frx, shiftdone) + begin + -- start shifting + if (nreset = '0' or shiftdone = '1') then + start_shifting <= '0'; + elsif (rising_edge(ndev_sel) and addr="00" and (frx='1' or is_read='0')) then + -- access to register 00, either write (is_read=0) or fast receive bit set (frx) + -- then both types of access (write but also read) + start_shifting <= '1'; + end if; + end process; + + -------------------------- + -- spiclk - spi clock generation + -- spiclk is still 2 times the freq. than sclk + clksrc <= phi0 when (ece = '0') else clk; + + -- is a pulse signal to allow for divisor==0 + --shiftclk <= clksrc when divcnt = "000000" else '0'; + shiftclk <= clksrc when bsy = '1' else '0'; + +-- clkgen: process(nreset, divisor, clksrc) +-- begin +-- if (nreset = '0') then +-- divcnt <= divisor; +-- elsif (falling_edge(clksrc)) then +-- if (shiftclk = '1') then +-- divcnt <= divisor; +-- else +-- divcnt <= divcnt - 1; +-- end if; +-- end if; +-- end process; + + -------------------------- + -- interface section + -- inputs + int_miso <= (miso and not slavesel); + + -- outputs + nsel <= slavesel; + + tc_proc: process (ndev_sel, shiftdone) + begin + if (shiftdone = '1') then + tc <= '1'; + elsif (rising_edge(ndev_sel) and addr="00") then + tc <= '0'; + end if; + end process; + + -------------------------- + -- cpu register section + -- cpu read + cpu_read: process(addr, spidatain, tc, bsy, frx, + ece, divisor, slavesel, wp, card, inited) + begin + case addr is + when "00" => -- read SPI data in + data_out <= spidatain; + when "01" => -- read status register + data_out(0) <= '0'; + data_out(1) <= '0'; + data_out(2) <= ece; + data_out(3) <= '0'; + data_out(4) <= frx; + data_out(5) <= bsy; + data_out(6) <= '0'; + data_out(7) <= tc; + when "10" => -- read sclk divisor + data_out(DIV_WIDTH-1 downto 0) <= divisor; + data_out(7 downto 3) <= (others => '0'); + when "11" => -- read slave select / slave interrupt state + data_out(0) <= slavesel; + data_out(4 downto 1) <= (others => '0'); + data_out(5) <= wp; + data_out(6) <= card; + data_out(7) <= inited; + when others => + data_out <= (others => '0'); + end case; + end process; + + -- cpu write + cpu_write: process(nreset, ndev_sel, is_read, addr, data_in, card, inited) + begin + if (nreset = '0') then + ece <= '0'; + frx <= '0'; + slavesel <= '1'; + divisor <= (others => '0'); + spidataout <= (others => '1'); + inited <= '0'; + elsif (card = '1') then + inited <= '0'; + elsif (rising_edge(ndev_sel) and is_read = '0') then + case addr is + when "00" => -- write SPI data out (see other process above) + spidataout <= data_in; + when "01" => -- write status register + ece <= data_in(2); + frx <= data_in(4); + -- no bit 5 - 7 + when "10" => -- write divisor + divisor <= data_in(DIV_WIDTH-1 downto 0); + when "11" => -- write slave select / slave interrupt enable + slavesel <= data_in(0); + -- no bit 1 - 6 + inited <= data_in(7); + when others => + end case; + end if; + end process; + +end Behavioral; + diff --git a/VHDL/in_buf.jhd b/VHDL/in_buf.jhd deleted file mode 100644 index c7e41e4..0000000 --- a/VHDL/in_buf.jhd +++ /dev/null @@ -1 +0,0 @@ -MODULE in_buf diff --git a/VHDL/in_buf.sch b/VHDL/in_buf.sch deleted file mode 100644 index b942ea5..0000000 --- a/VHDL/in_buf.sch +++ /dev/null @@ -1,12 +0,0 @@ - - - - - - - - - - - - \ No newline at end of file diff --git a/VHDL/io_buffers.sch b/VHDL/io_buffers.sch deleted file mode 100644 index 4afd2dd..0000000 --- a/VHDL/io_buffers.sch +++ /dev/null @@ -1,466 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - - - - 2017-10-8T19:38:25 - - - - - - - - - - - - - - - - - 2017-10-8T19:42:44 - - - - - - - - - - - - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/VHDL/sch2HdlBatchFile b/VHDL/sch2HdlBatchFile deleted file mode 100644 index e69de29..0000000