mirror of
https://github.com/freitz85/AppleIISd.git
synced 2024-06-01 14:41:35 +00:00
214 lines
7.9 KiB
Plaintext
214 lines
7.9 KiB
Plaintext
Release 6.3.03i - xst G.38
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Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to __projnav
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CPU : 0.00 / 0.25 s | Elapsed : 0.00 / 0.00 s
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--> Parameter xsthdpdir set to ./xst
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CPU : 0.00 / 0.25 s | Elapsed : 0.00 / 0.00 s
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--> Reading design: spi6502b.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) HDL Analysis
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4) HDL Synthesis
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5) Advanced HDL Synthesis
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5.1) HDL Synthesis Report
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6) Low Level Synthesis
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7) Final Report
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : spi6502b.prj
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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Verilog Include Directory :
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---- Target Parameters
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Output File Name : spi6502b
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Output Format : NGC
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Target Device : xc9500xl
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---- Source Options
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Top Module Name : spi6502b
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Mux Extraction : YES
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Resource Sharing : YES
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---- Target Options
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Add IO Buffers : YES
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Equivalent register Removal : YES
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MACRO Preserve : YES
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XOR Preserve : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : YES
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RTL Output : Yes
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Hierarchy Separator : _
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Bus Delimiter : <>
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Case Specifier : maintain
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---- Other Options
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lso : spi6502b.lso
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verilog2001 : YES
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Clock Enable : YES
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wysiwyg : NO
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling vhdl file C:/sources/AppleIISd/SPI6502B1.1.vhd in Library work.
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Entity <spi6502b> (Architecture <behavioral>) compiled.
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing Entity <spi6502b> (Architecture <behavioral>).
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INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 203: Mux is complete : default of case is discarded
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INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 316: Mux is complete : default of case is discarded
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Entity <spi6502b> analyzed. Unit <spi6502b> generated.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Synthesizing Unit <spi6502b>.
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Related source file is C:/sources/AppleIISd/SPI6502B1.1.vhd.
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Found 8-bit tristate buffer for signal <cpu_d>.
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Found 1-bit tristate buffer for signal <cpu_Nirq>.
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Found 1-bit tristate buffer for signal <spi_mosi>.
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Found 1-bit xor3 for signal <$n0040> created at line 206.
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Found 4-bit adder for signal <$n0047> created at line 160.
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Found 1-bit register for signal <cpha>.
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Found 1-bit register for signal <cpol>.
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Found 3-bit down counter for signal <divcnt>.
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Found 3-bit register for signal <divisor>.
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Found 1-bit register for signal <ece>.
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Found 1-bit register for signal <frx>.
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Found 1-bit register for signal <ier>.
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Found 1-bit register for signal <int_mosi>.
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Found 1-bit register for signal <int_sclk>.
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Found 4-bit register for signal <shiftcnt>.
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Found 1-bit register for signal <shiftdone>.
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Found 1-bit register for signal <shifting2>.
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Found 1-bit register for signal <slaveinten>.
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Found 1-bit register for signal <slavesel>.
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Found 8-bit register for signal <spidatain>.
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Found 8-bit register for signal <spidataout>.
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Found 1-bit register for signal <start_shifting>.
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Found 1-bit register for signal <tc>.
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Found 1-bit register for signal <tmo>.
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Found 24 1-bit 2-to-1 multiplexers.
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Summary:
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inferred 1 Counter(s).
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inferred 20 D-type flip-flop(s).
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inferred 1 Adder/Subtracter(s).
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inferred 10 Tristate(s).
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Unit <spi6502b> synthesized.
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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Advanced RAM inference ...
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Advanced multiplier inference ...
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Advanced Registered AddSub inference ...
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Dynamic shift register inference ...
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Adders/Subtractors : 1
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4-bit adder : 1
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# Registers : 25
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1-bit register : 22
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8-bit register : 1
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3-bit register : 1
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4-bit register : 1
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# Multiplexers : 12
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2-to-1 multiplexer : 12
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# Tristates : 3
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1-bit tristate buffer : 2
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8-bit tristate buffer : 1
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# Xors : 1
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1-bit xor3 : 1
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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Optimizing unit <spi6502b> ...
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=========================================================================
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* Final Report *
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=========================================================================
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Final Results
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RTL Top Level Output File Name : spi6502b.ngr
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Top Level Output File Name : spi6502b
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Output Format : NGC
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Optimization Goal : Speed
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Keep Hierarchy : YES
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Target Technology : xc9500xl
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Macro Preserve : YES
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XOR Preserve : YES
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Clock Enable : YES
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wysiwyg : NO
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Design Statistics
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# IOs : 23
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Macro Statistics :
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# Registers : 60
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# 1-bit register : 60
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# Tristates : 3
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# 1-bit tristate buffer : 2
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# 8-bit tristate buffer : 1
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# Xors : 5
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# 1-bit xor2 : 5
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Cell Usage :
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# BELS : 252
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# AND2 : 119
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# AND3 : 5
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# AND4 : 1
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# GND : 1
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# INV : 77
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# OR2 : 42
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# OR3 : 1
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# VCC : 1
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# XOR2 : 5
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# FlipFlops/Latches : 37
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# FD : 1
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# FDC : 5
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# FDCE : 27
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# FDCP : 1
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# FDP : 1
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# FDPE : 2
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# IO Buffers : 23
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# IBUF : 10
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# IOBUFE : 8
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# OBUF : 3
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# OBUFE : 2
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=========================================================================
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CPU : 0.65 / 1.07 s | Elapsed : 0.00 / 1.00 s
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-->
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Total memory usage is 68376 kilobytes
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