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add new cpu
This commit is contained in:
Stefan
parent
ee98dafec8
commit
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666
src/cpu/t65/T65.vhd
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666
src/cpu/t65/T65.vhd
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@ -0,0 +1,666 @@
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-- ****
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-- T65(b) core. In an effort to merge and maintain bug fixes ....
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--
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-- Ver 313 WoS January 2015
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-- Fixed issue that NMI has to be first if issued the same time as a BRK instruction is latched in
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-- Now all Lorenz CPU tests on FPGAARCADE C64 core (sources used: SVN version 1021) are OK! :D :D :D
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-- This is just a starting point to go for optimizations and detailed fixes (the Lorenz test can't find)
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--
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-- Ver 312 WoS January 2015
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-- Undoc opcode timing fixes for $B3 (LAX iy) and $BB (LAS ay)
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-- Added comments in MCode section to find handling of individual opcodes more easily
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-- All "basic" Lorenz instruction test (individual functional checks, CPUTIMING check) work now with
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-- actual FPGAARCADE C64 core (sources used: SVN version 1021).
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--
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-- Ver 305, 306, 307, 308, 309, 310, 311 WoS January 2015
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-- Undoc opcode fixes (now all Lorenz test on instruction functionality working, except timing issues on $B3 and $BB):
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-- SAX opcode
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-- SHA opcode
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-- SHX opcode
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-- SHY opcode
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-- SHS opcode
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-- LAS opcode
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-- alternate SBC opcode
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-- fixed NOP with immediate param (caused Lorenz trap test to fail)
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-- IRQ and NMI timing fixes (in conjuction with branches)
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--
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-- Ver 304 WoS December 2014
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-- Undoc opcode fixes:
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-- ARR opcode
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-- ANE/XAA opcode
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-- Corrected issue with NMI/IRQ prio (when asserted the same time)
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--
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-- Ver 303 ost(ML) July 2014
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-- (Sorry for some scratchpad comments that may make little sense)
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-- Mods and some 6502 undocumented instructions.
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-- Not correct opcodes acc. to Lorenz tests (incomplete list):
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-- NOPN (nop)
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-- NOPZX (nop + byte 172)
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-- NOPAX (nop + word da ... da: byte 0)
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-- ASOZ (byte $07 + byte 172)
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--
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-- Ver 303,302 WoS April 2014
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-- Bugfixes for NMI from foft
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-- Bugfix for BRK command (and its special flag)
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--
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-- Ver 300,301 WoS January 2014
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-- More merging
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-- Bugfixes by ehenciak added, started tidyup *bust*
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--
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-- MikeJ March 2005
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-- Latest version from www.fpgaarcade.com (original www.opencores.org)
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-- ****
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--
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-- 65xx compatible microprocessor core
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--
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-- FPGAARCADE SVN: $Id: T65.vhd 1347 2015-05-27 20:07:34Z wolfgang.scherr $
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--
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-- Copyright (c) 2002...2015
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-- Daniel Wallner (jesus <at> opencores <dot> org)
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-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
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-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
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-- Morten Leikvoll ()
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author(s), but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- ----- IMPORTANT NOTES -----
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--
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-- Limitations:
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-- 65C02 and 65C816 modes are incomplete (and definitely untested after all 6502 undoc fixes)
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-- 65C02 supported : inc, dec, phx, plx, phy, ply
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-- 65D02 missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8
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-- Some interface signals behave incorrect
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-- NMI interrupt handling not nice, needs further rework (to cycle-based encoding).
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--
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-- Usage:
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-- The enable signal allows clock gating / throttling without using the ready signal.
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-- Set it to constant '1' when using the Clk input as the CPU clock directly.
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--
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-- TAKE CARE you route the DO signal back to the DI signal while R_W_n='0',
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-- otherwise some undocumented opcodes won't work correctly.
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-- EXAMPLE:
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-- CPU : entity work.T65
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-- port map (
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-- R_W_n => cpu_rwn_s,
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-- [....all other ports....]
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-- DI => cpu_din_s,
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-- DO => cpu_dout_s
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-- );
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-- cpu_din_s <= cpu_dout_s when cpu_rwn_s='0' else
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-- [....other sources from peripherals and memories...]
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--
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-- ----- IMPORTANT NOTES -----
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.T65_Pack.all;
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entity T65 is
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port(
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Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
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Res_n : in std_logic;
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Enable : in std_logic;
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Clk : in std_logic;
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Rdy : in std_logic;
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Abort_n : in std_logic;
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IRQ_n : in std_logic;
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NMI_n : in std_logic;
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SO_n : in std_logic;
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R_W_n : out std_logic;
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Sync : out std_logic;
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EF : out std_logic;
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MF : out std_logic;
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XF : out std_logic;
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ML_n : out std_logic;
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VP_n : out std_logic;
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VDA : out std_logic;
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VPA : out std_logic;
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A : out std_logic_vector(23 downto 0);
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DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0);
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DEBUG : out T_t65_dbg
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);
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end T65;
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architecture rtl of T65 is
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-- Registers
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signal ABC, X, Y, D : std_logic_vector(15 downto 0);
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signal P, AD, DL : std_logic_vector(7 downto 0) := x"00";
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signal PwithB : std_logic_vector(7 downto 0);--ML:New way to push P with correct B state to stack
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signal BAH : std_logic_vector(7 downto 0);
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signal BAL : std_logic_vector(8 downto 0);
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signal PBR : std_logic_vector(7 downto 0);
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signal DBR : std_logic_vector(7 downto 0);
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signal PC : unsigned(15 downto 0);
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signal S : unsigned(15 downto 0);
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signal EF_i : std_logic;
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signal MF_i : std_logic;
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signal XF_i : std_logic;
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signal IR : std_logic_vector(7 downto 0);
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signal MCycle : std_logic_vector(2 downto 0);
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signal Mode_r : std_logic_vector(1 downto 0);
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signal ALU_Op_r : T_ALU_Op;
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signal Write_Data_r : T_Write_Data;
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signal Set_Addr_To_r : T_Set_Addr_To;
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signal PCAdder : unsigned(8 downto 0);
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signal RstCycle : std_logic;
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signal IRQCycle : std_logic;
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signal NMICycle : std_logic;
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signal SO_n_o : std_logic;
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signal IRQ_n_o : std_logic;
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signal NMI_n_o : std_logic;
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signal NMIAct : std_logic;
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signal Break : std_logic;
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-- ALU signals
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signal BusA : std_logic_vector(7 downto 0);
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signal BusA_r : std_logic_vector(7 downto 0);
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signal BusB : std_logic_vector(7 downto 0);
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signal BusB_r : std_logic_vector(7 downto 0);
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signal ALU_Q : std_logic_vector(7 downto 0);
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signal P_Out : std_logic_vector(7 downto 0);
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-- Micro code outputs
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signal LCycle : std_logic_vector(2 downto 0);
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signal ALU_Op : T_ALU_Op;
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signal Set_BusA_To : T_Set_BusA_To;
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signal Set_Addr_To : T_Set_Addr_To;
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signal Write_Data : T_Write_Data;
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signal Jump : std_logic_vector(1 downto 0);
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signal BAAdd : std_logic_vector(1 downto 0);
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signal BreakAtNA : std_logic;
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signal ADAdd : std_logic;
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signal AddY : std_logic;
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signal PCAdd : std_logic;
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signal Inc_S : std_logic;
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signal Dec_S : std_logic;
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signal LDA : std_logic;
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signal LDP : std_logic;
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signal LDX : std_logic;
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signal LDY : std_logic;
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signal LDS : std_logic;
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signal LDDI : std_logic;
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signal LDALU : std_logic;
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signal LDAD : std_logic;
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signal LDBAL : std_logic;
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signal LDBAH : std_logic;
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signal SaveP : std_logic;
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signal Write : std_logic;
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signal Res_n_i : std_logic;
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signal Res_n_d : std_logic;
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signal really_rdy : std_logic;
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signal WRn_i : std_logic;
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signal NMI_entered : std_logic;
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begin
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-- gate Rdy with read/write to make an "OK, it's really OK to stop the processor
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really_rdy <= Rdy or not(WRn_i);
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Sync <= '1' when MCycle = "000" else '0';
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EF <= EF_i;
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MF <= MF_i;
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XF <= XF_i;
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R_W_n <= WRn_i;
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ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
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VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
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VDA <= '1' when Set_Addr_To_r /= Set_Addr_To_PBR else '0';
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VPA <= '1' when Jump(1) = '0' else '0';
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-- debugging signals
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DEBUG.I <= IR;
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DEBUG.A <= ABC(7 downto 0);
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DEBUG.X <= X(7 downto 0);
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DEBUG.Y <= Y(7 downto 0);
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DEBUG.S <= std_logic_vector(S(7 downto 0));
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DEBUG.P <= P;
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mcode : entity work.T65_MCode
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port map(
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--inputs
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Mode => Mode_r,
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IR => IR,
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MCycle => MCycle,
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P => P,
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--outputs
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LCycle => LCycle,
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ALU_Op => ALU_Op,
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Set_BusA_To => Set_BusA_To,
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Set_Addr_To => Set_Addr_To,
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Write_Data => Write_Data,
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Jump => Jump,
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BAAdd => BAAdd,
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BreakAtNA => BreakAtNA,
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ADAdd => ADAdd,
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AddY => AddY,
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PCAdd => PCAdd,
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Inc_S => Inc_S,
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Dec_S => Dec_S,
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LDA => LDA,
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LDP => LDP,
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LDX => LDX,
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LDY => LDY,
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LDS => LDS,
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LDDI => LDDI,
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LDALU => LDALU,
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LDAD => LDAD,
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LDBAL => LDBAL,
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LDBAH => LDBAH,
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SaveP => SaveP,
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Write => Write
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);
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alu : entity work.T65_ALU
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port map(
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Mode => Mode_r,
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Op => ALU_Op_r,
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BusA => BusA_r,
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BusB => BusB,
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P_In => P,
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P_Out => P_Out,
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Q => ALU_Q
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);
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-- the 65xx design requires at least two clock cycles before
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-- starting its reset sequence (according to datasheet)
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process (Res_n_i, Clk)
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begin
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if Res_n = '0' then
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Res_n_i <= '0';
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Res_n_d <= '0';
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elsif Clk'event and Clk = '1' then
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Res_n_i <= Res_n_d;
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Res_n_d <= '1';
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end if;
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end process;
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process (Res_n_i, Clk)
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begin
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if Res_n_i = '0' then
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PC <= (others => '0'); -- Program Counter
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IR <= "00000000";
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S <= (others => '0'); -- Dummy
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D <= (others => '0');
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PBR <= (others => '0');
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DBR <= (others => '0');
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Mode_r <= (others => '0');
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ALU_Op_r <= ALU_OP_BIT;
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Write_Data_r <= Write_Data_DL;
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Set_Addr_To_r <= Set_Addr_To_PBR;
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WRn_i <= '1';
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EF_i <= '1';
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MF_i <= '1';
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XF_i <= '1';
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elsif Clk'event and Clk = '1' then
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if (Enable = '1') then
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if (really_rdy = '1') then
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WRn_i <= not Write or RstCycle;
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D <= (others => '1'); -- Dummy
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PBR <= (others => '1'); -- Dummy
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DBR <= (others => '1'); -- Dummy
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EF_i <= '0'; -- Dummy
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MF_i <= '0'; -- Dummy
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XF_i <= '0'; -- Dummy
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if MCycle = "000" then
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Mode_r <= Mode;
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if IRQCycle = '0' and NMICycle = '0' then
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PC <= PC + 1;
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end if;
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if IRQCycle = '1' or NMICycle = '1' then
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IR <= "00000000";
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else
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IR <= DI;
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end if;
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if LDS = '1' then -- LAS won't work properly if not limited to machine cycle 0
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S(7 downto 0) <= unsigned(ALU_Q);
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end if;
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end if;
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ALU_Op_r <= ALU_Op;
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Write_Data_r <= Write_Data;
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if Break = '1' then
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Set_Addr_To_r <= Set_Addr_To_PBR;
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else
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Set_Addr_To_r <= Set_Addr_To;
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end if;
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if Inc_S = '1' then
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S <= S + 1;
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end if;
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if Dec_S = '1' and RstCycle = '0' then
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S <= S - 1;
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end if;
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if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
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PC <= PC + 1;
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end if;
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--
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-- jump control logic
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--
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case Jump is
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when "01" =>
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PC <= PC + 1;
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when "10" =>
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PC <= unsigned(DI & DL);
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when "11" =>
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if PCAdder(8) = '1' then
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if DL(7) = '0' then
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PC(15 downto 8) <= PC(15 downto 8) + 1;
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else
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PC(15 downto 8) <= PC(15 downto 8) - 1;
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end if;
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end if;
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PC(7 downto 0) <= PCAdder(7 downto 0);
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when others => null;
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end case;
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end if;
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end if;
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end if;
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end process;
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PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
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else "0" & PC(7 downto 0);
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process (Res_n_i, Clk)
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variable tmpP:std_logic_vector(7 downto 0);--Lets try to handle loading P at mcycle=0 and set/clk flags at same cycle
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begin
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if Res_n_i = '0' then
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P <= x"00"; -- ensure we have nothing set on reset
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elsif Clk'event and Clk = '1' then
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tmpP:=P;
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if (Enable = '1') then
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if (really_rdy = '1') then
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if MCycle = "000" then
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if LDA = '1' then
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ABC(7 downto 0) <= ALU_Q;
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end if;
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if LDX = '1' then
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X(7 downto 0) <= ALU_Q;
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end if;
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if LDY = '1' then
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Y(7 downto 0) <= ALU_Q;
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end if;
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if (LDA or LDX or LDY) = '1' then
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tmpP:=P_Out;
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end if;
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end if;
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if SaveP = '1' then
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tmpP:=P_Out;
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end if;
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if LDP = '1' then
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tmpP:=ALU_Q;
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end if;
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if IR(4 downto 0) = "11000" then
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case IR(7 downto 5) is
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when "000" =>--0x18(clc)
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tmpP(Flag_C) := '0';
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when "001" =>--0x38(sec)
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tmpP(Flag_C) := '1';
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when "010" =>--0x58(cli)
|
||||
tmpP(Flag_I) := '0';
|
||||
when "011" =>--0x78(sei)
|
||||
tmpP(Flag_I) := '1';
|
||||
when "101" =>--0xb8(clv)
|
||||
tmpP(Flag_V) := '0';
|
||||
when "110" =>--0xd8(cld)
|
||||
tmpP(Flag_D) := '0';
|
||||
when "111" =>--0xf8(sed)
|
||||
tmpP(Flag_D) := '1';
|
||||
when others =>
|
||||
end case;
|
||||
end if;
|
||||
tmpP(Flag_B) := '1';
|
||||
if IR = "00000000" and MCycle = "100" and RstCycle = '0' then
|
||||
--This should happen after P has been pushed to stack
|
||||
tmpP(Flag_I) := '1';
|
||||
end if;
|
||||
if SO_n_o = '1' and SO_n = '0' then
|
||||
tmpP(Flag_V) := '1';
|
||||
end if;
|
||||
if RstCycle = '1' then
|
||||
tmpP(Flag_I) := '0';
|
||||
tmpP(Flag_D) := '0';
|
||||
end if;
|
||||
tmpP(Flag_1) := '1';
|
||||
|
||||
P<=tmpP;--new way
|
||||
|
||||
SO_n_o <= SO_n;
|
||||
if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510), not best way yet, though - but works...
|
||||
IRQ_n_o <= IRQ_n;
|
||||
end if;
|
||||
end if;
|
||||
-- detect nmi even if not rdy
|
||||
if IR(4 downto 0)/="10000" or Jump/="01" then -- delay interrupts during branches (checked with Lorenz test and real 6510) not best way yet, though - but works...
|
||||
NMI_n_o <= NMI_n;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---------------------------------------------------------------------------
|
||||
--
|
||||
-- Buses
|
||||
--
|
||||
---------------------------------------------------------------------------
|
||||
|
||||
process (Res_n_i, Clk)
|
||||
begin
|
||||
if Res_n_i = '0' then
|
||||
BusA_r <= (others => '0');
|
||||
BusB <= (others => '0');
|
||||
BusB_r <= (others => '0');
|
||||
AD <= (others => '0');
|
||||
BAL <= (others => '0');
|
||||
BAH <= (others => '0');
|
||||
DL <= (others => '0');
|
||||
elsif Clk'event and Clk = '1' then
|
||||
if (Enable = '1') then
|
||||
NMI_entered <= '0';
|
||||
if (really_rdy = '1') then
|
||||
BusA_r <= BusA;
|
||||
BusB <= DI;
|
||||
|
||||
-- not really nice, but no better way found yet !
|
||||
if Set_Addr_To_r = Set_Addr_To_PBR or Set_Addr_To_r = Set_Addr_To_ZPG then
|
||||
BusB_r <= std_logic_vector(unsigned(DI(7 downto 0)) + 1); -- required for SHA
|
||||
end if;
|
||||
|
||||
case BAAdd is
|
||||
when "01" =>
|
||||
-- BA Inc
|
||||
AD <= std_logic_vector(unsigned(AD) + 1);
|
||||
BAL <= std_logic_vector(unsigned(BAL) + 1);
|
||||
when "10" =>
|
||||
-- BA Add
|
||||
BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
|
||||
when "11" =>
|
||||
-- BA Adj
|
||||
if BAL(8) = '1' then
|
||||
BAH <= std_logic_vector(unsigned(BAH) + 1);
|
||||
end if;
|
||||
when others =>
|
||||
end case;
|
||||
|
||||
-- modified to use Y register as well
|
||||
if ADAdd = '1' then
|
||||
if (AddY = '1') then
|
||||
AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
|
||||
else
|
||||
AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if IR = "00000000" then
|
||||
BAL <= (others => '1');
|
||||
BAH <= (others => '1');
|
||||
if RstCycle = '1' then
|
||||
BAL(2 downto 0) <= "100";
|
||||
elsif NMICycle = '1' or (NMIAct = '1' and MCycle="100") or NMI_entered='1' then
|
||||
BAL(2 downto 0) <= "010";
|
||||
if MCycle="100" then
|
||||
NMI_entered <= '1';
|
||||
end if;
|
||||
else
|
||||
BAL(2 downto 0) <= "110";
|
||||
end if;
|
||||
if Set_addr_To_r = Set_Addr_To_BA then
|
||||
BAL(0) <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if LDDI = '1' then
|
||||
DL <= DI;
|
||||
end if;
|
||||
if LDALU = '1' then
|
||||
DL <= ALU_Q;
|
||||
end if;
|
||||
if LDAD = '1' then
|
||||
AD <= DI;
|
||||
end if;
|
||||
if LDBAL = '1' then
|
||||
BAL(7 downto 0) <= DI;
|
||||
end if;
|
||||
if LDBAH = '1' then
|
||||
BAH <= DI;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
|
||||
|
||||
with Set_BusA_To select
|
||||
BusA <=
|
||||
DI when Set_BusA_To_DI,
|
||||
ABC(7 downto 0) when Set_BusA_To_ABC,
|
||||
X(7 downto 0) when Set_BusA_To_X,
|
||||
Y(7 downto 0) when Set_BusA_To_Y,
|
||||
std_logic_vector(S(7 downto 0)) when Set_BusA_To_S,
|
||||
P when Set_BusA_To_P,
|
||||
ABC(7 downto 0) and DI when Set_BusA_To_DA,
|
||||
(ABC(7 downto 0) or x"ee") and DI when Set_BusA_To_DAO,--ee for OAL instruction. constant may be different on other platforms.TODO:Move to generics
|
||||
(ABC(7 downto 0) or x"ee") and DI and X(7 downto 0) when Set_BusA_To_DAX,--XAA, ee for OAL instruction. constant may be different on other platforms.TODO:Move to generics
|
||||
ABC(7 downto 0) and X(7 downto 0) when Set_BusA_To_AAX,--SAX, SHA
|
||||
(others => '-') when Set_BusA_To_DONTCARE;--Can probably remove this
|
||||
|
||||
with Set_Addr_To_r select
|
||||
A <=
|
||||
"0000000000000001" & std_logic_vector(S(7 downto 0)) when Set_Addr_To_SP,
|
||||
DBR & "00000000" & AD when Set_Addr_To_ZPG,
|
||||
"00000000" & BAH & BAL(7 downto 0) when Set_Addr_To_BA,
|
||||
PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when Set_Addr_To_PBR;
|
||||
|
||||
-- This is the P that gets pushed on stack with correct B flag. I'm not sure if NMI also clears B, but I guess it does.
|
||||
PwithB<=(P and x"ef") when (IRQCycle='1' or NMICycle='1') else P;
|
||||
|
||||
with Write_Data_r select
|
||||
DO <=
|
||||
DL when Write_Data_DL,
|
||||
ABC(7 downto 0) when Write_Data_ABC,
|
||||
X(7 downto 0) when Write_Data_X,
|
||||
Y(7 downto 0) when Write_Data_Y,
|
||||
std_logic_vector(S(7 downto 0)) when Write_Data_S,
|
||||
PwithB when Write_Data_P,
|
||||
std_logic_vector(PC(7 downto 0)) when Write_Data_PCL,
|
||||
std_logic_vector(PC(15 downto 8)) when Write_Data_PCH,
|
||||
ABC(7 downto 0) and X(7 downto 0) when Write_Data_AX,
|
||||
ABC(7 downto 0) and X(7 downto 0) and BusB_r(7 downto 0) when Write_Data_AXB, -- no better way found yet...
|
||||
X(7 downto 0) and BusB_r(7 downto 0) when Write_Data_XB, -- no better way found yet...
|
||||
Y(7 downto 0) and BusB_r(7 downto 0) when Write_Data_YB, -- no better way found yet...
|
||||
(others=>'-') when Write_Data_DONTCARE;--Can probably remove this
|
||||
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
--
|
||||
-- Main state machine
|
||||
--
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
process (Res_n_i, Clk)
|
||||
begin
|
||||
if Res_n_i = '0' then
|
||||
MCycle <= "001";
|
||||
RstCycle <= '1';
|
||||
IRQCycle <= '0';
|
||||
NMICycle <= '0';
|
||||
NMIAct <= '0';
|
||||
elsif Clk'event and Clk = '1' then
|
||||
if (Enable = '1') then
|
||||
if (really_rdy = '1') then
|
||||
if MCycle = LCycle or Break = '1' then
|
||||
MCycle <= "000";
|
||||
RstCycle <= '0';
|
||||
IRQCycle <= '0';
|
||||
NMICycle <= '0';
|
||||
if NMIAct = '1' and IR/=x"00" then -- delay NMI further if we just executed a BRK
|
||||
NMICycle <= '1';
|
||||
NMIAct <= '0'; -- reset NMI edge detector if we start processing the NMI
|
||||
elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
|
||||
IRQCycle <= '1';
|
||||
end if;
|
||||
else
|
||||
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
|
||||
end if;
|
||||
end if;
|
||||
--detect NMI even if not rdy
|
||||
if NMI_n_o = '1' and (NMI_n = '0' and (IR(4 downto 0)/="10000" or Jump/="01")) then -- branches have influence on NMI start (not best way yet, though - but works...)
|
||||
NMIAct <= '1';
|
||||
end if;
|
||||
-- we entered NMI during BRK instruction
|
||||
if NMI_entered='1' then
|
||||
NMIAct <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
Loading…
Reference in New Issue
Block a user