// Copyright (C) 2022  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and any partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition"

// DATE "02/28/2023 11:21:31"

// 
// Device: Altera EPM240T100C5 Package TQFP100
// 

// 
// This Verilog file should be used for Questa Intel FPGA (Verilog) only
// 

`timescale 1 ps/ 1 ps

module GR8RAM (
	C25M,
	PHI0,
	nRES,
	nRESout,
	SetFW,
	INTin,
	INTout,
	DMAin,
	DMAout,
	nNMIout,
	nIRQout,
	nRDYout,
	nINHout,
	RWout,
	nDMAout,
	RA,
	nWE,
	RD,
	RAdir,
	RDdir,
	nIOSEL,
	nDEVSEL,
	nIOSTRB,
	SBA,
	SA,
	nRCS,
	nRAS,
	nCAS,
	nSWE,
	DQML,
	DQMH,
	RCKE,
	SD,
	nFCS,
	FCK,
	MISO,
	MOSI);
input 	C25M;
input 	PHI0;
input 	nRES;
output 	nRESout;
input 	[1:0] SetFW;
input 	INTin;
output 	INTout;
input 	DMAin;
output 	DMAout;
output 	nNMIout;
output 	nIRQout;
output 	nRDYout;
output 	nINHout;
output 	RWout;
output 	nDMAout;
input 	[15:0] RA;
input 	nWE;
inout 	[7:0] RD;
output 	RAdir;
output 	RDdir;
input 	nIOSEL;
input 	nDEVSEL;
input 	nIOSTRB;
output 	[1:0] SBA;
output 	[12:0] SA;
output 	nRCS;
output 	nRAS;
output 	nCAS;
output 	nSWE;
output 	DQML;
output 	DQMH;
output 	RCKE;
inout 	[7:0] SD;
output 	nFCS;
output 	FCK;
input 	MISO;
inout 	MOSI;

// Design Ports Information


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \nIOSTRBr~regout ;
wire \RD[0]~0 ;
wire \RD[1]~1 ;
wire \RD[2]~2 ;
wire \RD[3]~3 ;
wire \RD[4]~4 ;
wire \RD[5]~5 ;
wire \RD[6]~6 ;
wire \RD[7]~7 ;
wire \SD[0]~0 ;
wire \SD[1]~1 ;
wire \SD[2]~2 ;
wire \SD[3]~3 ;
wire \SD[4]~4 ;
wire \SD[5]~5 ;
wire \SD[6]~6 ;
wire \SD[7]~7 ;
wire \MOSI~0 ;
wire \C25M~combout ;
wire \Equal1~0_combout ;
wire \PHI0~combout ;
wire \PHI0r1~regout ;
wire \nWE~combout ;
wire \PHI0r2~regout ;
wire \PS~0 ;
wire \Equal2~1_combout ;
wire \LS[1]~3 ;
wire \LS[2]~7 ;
wire \LS[2]~7COUT1_28 ;
wire \LS[3]~11 ;
wire \LS[3]~11COUT1_29 ;
wire \LS[4]~13 ;
wire \LS[4]~13COUT1_30 ;
wire \LS[5]~15 ;
wire \LS[5]~15COUT1_31 ;
wire \LS[6]~17 ;
wire \Equal3~0_combout ;
wire \LS[7]~19 ;
wire \LS[7]~19COUT1_32 ;
wire \LS[8]~21 ;
wire \LS[8]~21COUT1_33 ;
wire \LS[9]~23 ;
wire \LS[9]~23COUT1_34 ;
wire \LS[10]~1 ;
wire \LS[10]~1COUT1_35 ;
wire \LS[11]~5 ;
wire \Equal3~1_combout ;
wire \Equal3~2_combout ;
wire \Equal5~0_combout ;
wire \Equal6~0_combout ;
wire \LS[12]~9 ;
wire \LS[12]~9COUT1_36 ;
wire \IS.111~regout ;
wire \nRESout~reg0_regout ;
wire \INTin~combout ;
wire \DMAin~combout ;
wire \IS~17_combout ;
wire \IS~18_combout ;
wire \Equal3~3_combout ;
wire \Equal4~0 ;
wire \Equal3~4 ;
wire \IS~19_combout ;
wire \IS.110~regout ;
wire \SA[1]~3_combout ;
wire \Mux22~0_combout ;
wire \RAMRegSpecSEL~0 ;
wire \SA[1]~2_combout ;
wire \Mux24~0_combout ;
wire \Mux24~1_combout ;
wire \nRES~combout ;
wire \nRESr~regout ;
wire \nDEVSEL~combout ;
wire \nRCS~0_combout ;
wire \nWEr~regout ;
wire \Equal19~0_combout ;
wire \always9~1_combout ;
wire \RAMRegSpecSEL~1 ;
wire \always9~3_combout ;
wire \always9~4_combout ;
wire \always9~5_combout ;
wire \AddrIncL~regout ;
wire \Addr[0]~47 ;
wire \Addr[0]~47COUT1_61 ;
wire \Addr[1]~5 ;
wire \Addr[1]~5COUT1_62 ;
wire \Addr[2]~9 ;
wire \Addr[2]~9COUT1_63 ;
wire \Addr[3]~13 ;
wire \Addr[3]~13COUT1_64 ;
wire \Addr[4]~17 ;
wire \Addr[5]~21 ;
wire \Addr[5]~21COUT1_65 ;
wire \Addr[6]~25 ;
wire \Addr[6]~25COUT1_66 ;
wire \AddrIncM~1_combout ;
wire \AddrIncM~0_combout ;
wire \AddrIncM~2_combout ;
wire \AddrIncM~regout ;
wire \Addr[8]~33 ;
wire \Addr[8]~33COUT1_55 ;
wire \Addr[9]~37 ;
wire \Addr[9]~37COUT1_56 ;
wire \Addr[10]~3 ;
wire \Addr[10]~3COUT1_57 ;
wire \Mux23~0_combout ;
wire \Mux23~1_combout ;
wire \nIOSEL~combout ;
wire \REGEN~regout ;
wire \CXXXr~regout ;
wire \Equal9~0 ;
wire \always9~0_combout ;
wire \SetFWLoaded~regout ;
wire \always9~2_combout ;
wire \AddrIncH~0_combout ;
wire \Addr[11]~7 ;
wire \Addr[11]~7COUT1_58 ;
wire \Addr[12]~11 ;
wire \Addr[13]~15 ;
wire \Addr[13]~15COUT1_59 ;
wire \AddrIncH~1_combout ;
wire \AddrIncH~2_combout ;
wire \Addr[14]~19 ;
wire \Addr[14]~19COUT1_60 ;
wire \AddrIncH~regout ;
wire \Addr[16]~27 ;
wire \Addr[16]~27COUT1_49 ;
wire \Addr[17]~31 ;
wire \Addr[17]~31COUT1_50 ;
wire \Addr[18]~35 ;
wire \Addr[18]~35COUT1_51 ;
wire \Addr[19]~39 ;
wire \Addr[19]~39COUT1_52 ;
wire \Addr[20]~41 ;
wire \Addr[21]~43 ;
wire \Addr[21]~43COUT1_53 ;
wire \Addr[22]~45 ;
wire \Addr[22]~45COUT1_54 ;
wire \RAMSpecSEL~0 ;
wire \RAMSpecSEL~1_combout ;
wire \SA[1]~4_combout ;
wire \always8~0 ;
wire \nIOSTRB~combout ;
wire \always8~1 ;
wire \always8~2 ;
wire \always8~3 ;
wire \always8~4_combout ;
wire \IOROMEN~regout ;
wire \Equal16~0_combout ;
wire \Equal16~1_combout ;
wire \Equal16~2_combout ;
wire \comb~1_combout ;
wire \comb~0 ;
wire \comb~2_combout ;
wire \Mux14~2_combout ;
wire \Mux14~3_combout ;
wire \Mux14~0_combout ;
wire \Mux14~1_combout ;
wire \SBA[0]~reg0_regout ;
wire \Mux13~0_combout ;
wire \SBA[1]~reg0_regout ;
wire \Mux24~2 ;
wire \Mux24~3_combout ;
wire \SA[1]~5_combout ;
wire \SA[1]~6_combout ;
wire \SA[0]~reg0_regout ;
wire \Mux23~2 ;
wire \Mux23~3_combout ;
wire \SA[1]~reg0_regout ;
wire \Mux22~1 ;
wire \Bank~regout ;
wire \Mux22~2_combout ;
wire \Mux22~3_combout ;
wire \SA[2]~reg0_regout ;
wire \SA[3]~15_combout ;
wire \SA[3]~9_combout ;
wire \Mux21~3_combout ;
wire \Mux21~2 ;
wire \Mux21~4_combout ;
wire \SA[3]~8_combout ;
wire \SA[3]~reg0_regout ;
wire \Mux20~4_combout ;
wire \Mux20~2_combout ;
wire \Mux20~3_combout ;
wire \SA[4]~reg0_regout ;
wire \Mux19~3_combout ;
wire \Mux19~5_combout ;
wire \Mux19~2 ;
wire \Mux19~4_combout ;
wire \SA[5]~reg0_regout ;
wire \Mux18~4_combout ;
wire \Mux18~3_combout ;
wire \Mux18~2_combout ;
wire \SA[6]~reg0_regout ;
wire \Mux17~4_combout ;
wire \Mux17~2_combout ;
wire \Mux17~3_combout ;
wire \SA[7]~reg0_regout ;
wire \Mux16~3_combout ;
wire \Mux16~4_combout ;
wire \Mux16~2 ;
wire \SA[8]~reg0_regout ;
wire \SA[1]~7_combout ;
wire \SA~10_combout ;
wire \SA[9]~reg0_regout ;
wire \Mux15~0_combout ;
wire \Mux15~1_combout ;
wire \SA[10]~reg0_regout ;
wire \SA[11]~reg0_regout ;
wire \SA[12]~reg0_regout ;
wire \nRCS~3_combout ;
wire \nRCS~4_combout ;
wire \Mux12~1_combout ;
wire \Mux12~2_combout ;
wire \nRCS~5_combout ;
wire \Mux12~3_combout ;
wire \nRCS~1 ;
wire \IS.000~regout ;
wire \nRCS~2_combout ;
wire \Mux12~0_combout ;
wire \nRCS~reg0_regout ;
wire \nRAS~reg0_regout ;
wire \nCAS~reg0_regout ;
wire \IS.001~regout ;
wire \Selector0~0_combout ;
wire \nSWE~reg0_regout ;
wire \Equal1~1_combout ;
wire \Selector1~0_combout ;
wire \DQMH~0_combout ;
wire \DQML~reg0_regout ;
wire \Selector2~0_combout ;
wire \DQMH~reg0_regout ;
wire \Mux11~0_combout ;
wire \Mux11~1_combout ;
wire \Mux11~2_combout ;
wire \Mux11~3_combout ;
wire \Equal2~0_combout ;
wire \RCKE~reg0_regout ;
wire \IS.100~regout ;
wire \IS.101~regout ;
wire \FCS~regout ;
wire \FCKOE~regout ;
wire \FCKout~regout ;
wire \RDD[1]~23_combout ;
wire \RDD[1]~22_combout ;
wire \RDD~4_combout ;
wire \Equal20~0_combout ;
wire \RDD~6_combout ;
wire \RDD~8_combout ;
wire \RDD~10_combout ;
wire \RDD[4]~12_combout ;
wire \RDD~14_combout ;
wire \RDD[4]~13_combout ;
wire \RDD~16_combout ;
wire \RDD~18_combout ;
wire \RDD~20_combout ;
wire \SDOE~regout ;
wire \MISO~combout ;
wire \Mux2~0_combout ;
wire \Mux2~1_combout ;
wire \Mux2~2 ;
wire \Mux2~3_combout ;
wire \SA[1]~14_combout ;
wire \MOSIout~regout ;
wire \MOSIOE~regout ;
wire [1:0] SetFWr;
wire [15:0] \RA~combout ;
wire [1:0] \SetFW~combout ;
wire [3:0] PS;
wire [11:0] RAr;
wire [23:0] Addr;
wire [13:0] LS;
wire [7:0] RDD;
wire [3:0] nRESf;
wire [7:0] WRD;


// Location: PIN_86,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \RD[0]~I (
	.datain(RDD[0]),
	.oe(\comb~2_combout ),
	.combout(\RD[0]~0 ),
	.padio(RD[0]));
// synopsys translate_off
defparam \RD[0]~I .bus_hold = "true";
defparam \RD[0]~I .operation_mode = "bidir";
// synopsys translate_on

// Location: PIN_87,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \RD[1]~I (
	.datain(RDD[1]),
	.oe(\comb~2_combout ),
	.combout(\RD[1]~1 ),
	.padio(RD[1]));
// synopsys translate_off
defparam \RD[1]~I .bus_hold = "true";
defparam \RD[1]~I .operation_mode = "bidir";
// synopsys translate_on

// Location: PIN_88,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \RD[2]~I (
	.datain(RDD[2]),
	.oe(\comb~2_combout ),
	.combout(\RD[2]~2 ),
	.padio(RD[2]));
// synopsys translate_off
defparam \RD[2]~I .bus_hold = "true";
defparam \RD[2]~I .operation_mode = "bidir";
// synopsys translate_on

// Location: PIN_89,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \RD[3]~I (
	.datain(RDD[3]),
	.oe(\comb~2_combout ),
	.combout(\RD[3]~3 ),
	.padio(RD[3]));
// synopsys translate_off
defparam \RD[3]~I .bus_hold = "true";
defparam \RD[3]~I .operation_mode = "bidir";
// synopsys translate_on

// Location: PIN_90,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \RD[4]~I (
	.datain(RDD[4]),
	.oe(\comb~2_combout ),
	.combout(\RD[4]~4 ),
	.padio(RD[4]));
// synopsys translate_off
defparam \RD[4]~I .bus_hold = "true";
defparam \RD[4]~I .operation_mode = "bidir";
// synopsys translate_on

// Location: PIN_91,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \RD[5]~I (
	.datain(RDD[5]),
	.oe(\comb~2_combout ),
	.combout(\RD[5]~5 ),
	.padio(RD[5]));
// synopsys translate_off
defparam \RD[5]~I .bus_hold = "true";
defparam \RD[5]~I .operation_mode = "bidir";
// synopsys translate_on

// Location: PIN_92,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \RD[6]~I (
	.datain(RDD[6]),
	.oe(\comb~2_combout ),
	.combout(\RD[6]~6 ),
	.padio(RD[6]));
// synopsys translate_off
defparam \RD[6]~I .bus_hold = "true";
defparam \RD[6]~I .operation_mode = "bidir";
// synopsys translate_on

// Location: PIN_99,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \RD[7]~I (
	.datain(RDD[7]),
	.oe(\comb~2_combout ),
	.combout(\RD[7]~7 ),
	.padio(RD[7]));
// synopsys translate_off
defparam \RD[7]~I .bus_hold = "true";
defparam \RD[7]~I .operation_mode = "bidir";
// synopsys translate_on

// Location: PIN_50,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
maxii_io \SD[0]~I (
	.datain(WRD[0]),
	.oe(\SDOE~regout ),
	.combout(\SD[0]~0 ),
	.padio(SD[0]));
// synopsys translate_off
defparam \SD[0]~I .operation_mode = "bidir";
// synopsys translate_on

// Location: PIN_47,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
maxii_io \SD[1]~I (
	.datain(WRD[1]),
	.oe(\SDOE~regout ),
	.combout(\SD[1]~1 ),
	.padio(SD[1]));
// synopsys translate_off
defparam \SD[1]~I .operation_mode = "bidir";
// synopsys translate_on

// Location: PIN_56,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
maxii_io \SD[2]~I (
	.datain(WRD[2]),
	.oe(\SDOE~regout ),
	.combout(\SD[2]~2 ),
	.padio(SD[2]));
// synopsys translate_off
defparam \SD[2]~I .operation_mode = "bidir";
// synopsys translate_on

// Location: PIN_55,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
maxii_io \SD[3]~I (
	.datain(WRD[3]),
	.oe(\SDOE~regout ),
	.combout(\SD[3]~3 ),
	.padio(SD[3]));
// synopsys translate_off
defparam \SD[3]~I .operation_mode = "bidir";
// synopsys translate_on

// Location: PIN_51,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
maxii_io \SD[4]~I (
	.datain(WRD[4]),
	.oe(\SDOE~regout ),
	.combout(\SD[4]~4 ),
	.padio(SD[4]));
// synopsys translate_off
defparam \SD[4]~I .operation_mode = "bidir";
// synopsys translate_on

// Location: PIN_52,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
maxii_io \SD[5]~I (
	.datain(WRD[5]),
	.oe(\SDOE~regout ),
	.combout(\SD[5]~5 ),
	.padio(SD[5]));
// synopsys translate_off
defparam \SD[5]~I .operation_mode = "bidir";
// synopsys translate_on

// Location: PIN_53,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
maxii_io \SD[6]~I (
	.datain(WRD[6]),
	.oe(\SDOE~regout ),
	.combout(\SD[6]~6 ),
	.padio(SD[6]));
// synopsys translate_off
defparam \SD[6]~I .operation_mode = "bidir";
// synopsys translate_on

// Location: PIN_54,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
maxii_io \SD[7]~I (
	.datain(WRD[7]),
	.oe(\SDOE~regout ),
	.combout(\SD[7]~7 ),
	.padio(SD[7]));
// synopsys translate_off
defparam \SD[7]~I .operation_mode = "bidir";
// synopsys translate_on

// Location: PIN_15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \MOSI~I (
	.datain(\MOSIout~regout ),
	.oe(\MOSIOE~regout ),
	.combout(\MOSI~0 ),
	.padio(MOSI));
// synopsys translate_off
defparam \MOSI~I .bus_hold = "true";
defparam \MOSI~I .operation_mode = "bidir";
// synopsys translate_on

// Location: PIN_64,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \C25M~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\C25M~combout ),
	.padio(C25M));
// synopsys translate_off
defparam \C25M~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X7_Y2_N4
maxii_lcell \Equal1~0 (
// Equation(s):
// \Equal1~0_combout  = (!PS[1] & (((!PS[3]))))

	.clk(gnd),
	.dataa(PS[1]),
	.datab(vcc),
	.datac(PS[3]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Equal1~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Equal1~0 .lut_mask = "0505";
defparam \Equal1~0 .operation_mode = "normal";
defparam \Equal1~0 .output_mode = "comb_only";
defparam \Equal1~0 .register_cascade_mode = "off";
defparam \Equal1~0 .sum_lutc_input = "datac";
defparam \Equal1~0 .synch_mode = "off";
// synopsys translate_on

// Location: PIN_41,	 I/O Standard: 3.3V Schmitt Trigger Input,	 Current Strength: Default
maxii_io \PHI0~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\PHI0~combout ),
	.padio(PHI0));
// synopsys translate_off
defparam \PHI0~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X5_Y1_N6
maxii_lcell PHI0r1(
// Equation(s):
// \PS~0  = (((PHI0r1 & !\PHI0r2~regout )))
// \PHI0r1~regout  = DFFEAS(\PS~0 , GLOBAL(\C25M~combout ), VCC, , , \PHI0~combout , , , VCC)

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\PHI0~combout ),
	.datad(\PHI0r2~regout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\PS~0 ),
	.regout(\PHI0r1~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam PHI0r1.lut_mask = "00f0";
defparam PHI0r1.operation_mode = "normal";
defparam PHI0r1.output_mode = "reg_and_comb";
defparam PHI0r1.register_cascade_mode = "off";
defparam PHI0r1.sum_lutc_input = "qfbk";
defparam PHI0r1.synch_mode = "on";
// synopsys translate_on

// Location: PIN_43,	 I/O Standard: 3.3V Schmitt Trigger Input,	 Current Strength: Default
maxii_io \nWE~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\nWE~combout ),
	.padio(nWE));
// synopsys translate_off
defparam \nWE~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X5_Y1_N8
maxii_lcell PHI0r2(
// Equation(s):
// \comb~0  = (\PHI0~combout  & (((PHI0r2 & \nWE~combout ))))
// \PHI0r2~regout  = DFFEAS(\comb~0 , GLOBAL(\C25M~combout ), VCC, , , \PHI0r1~regout , , , VCC)

	.clk(\C25M~combout ),
	.dataa(\PHI0~combout ),
	.datab(vcc),
	.datac(\PHI0r1~regout ),
	.datad(\nWE~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\comb~0 ),
	.regout(\PHI0r2~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam PHI0r2.lut_mask = "a000";
defparam PHI0r2.operation_mode = "normal";
defparam PHI0r2.output_mode = "reg_and_comb";
defparam PHI0r2.register_cascade_mode = "off";
defparam PHI0r2.sum_lutc_input = "qfbk";
defparam PHI0r2.synch_mode = "on";
// synopsys translate_on

// Location: LC_X6_Y1_N1
maxii_lcell \PS[0] (
// Equation(s):
// PS[0] = DFFEAS((!PS[0] & (((\PS~0 ) # (PS[2])) # (!\Equal1~0_combout ))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(\Equal1~0_combout ),
	.datab(\PS~0 ),
	.datac(PS[2]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(PS[0]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \PS[0] .lut_mask = "00fd";
defparam \PS[0] .operation_mode = "normal";
defparam \PS[0] .output_mode = "reg_only";
defparam \PS[0] .register_cascade_mode = "off";
defparam \PS[0] .sum_lutc_input = "datac";
defparam \PS[0] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y4_N8
maxii_lcell \PS[1] (
// Equation(s):
// PS[1] = DFFEAS(PS[1] $ ((((PS[0])))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(PS[1]),
	.datab(vcc),
	.datac(vcc),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(PS[1]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \PS[1] .lut_mask = "55aa";
defparam \PS[1] .operation_mode = "normal";
defparam \PS[1] .output_mode = "reg_only";
defparam \PS[1] .register_cascade_mode = "off";
defparam \PS[1] .sum_lutc_input = "datac";
defparam \PS[1] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y1_N2
maxii_lcell \PS[2] (
// Equation(s):
// PS[2] = DFFEAS((PS[2] $ (((PS[1] & PS[0])))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(PS[2]),
	.datac(PS[1]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(PS[2]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \PS[2] .lut_mask = "3ccc";
defparam \PS[2] .operation_mode = "normal";
defparam \PS[2] .output_mode = "reg_only";
defparam \PS[2] .register_cascade_mode = "off";
defparam \PS[2] .sum_lutc_input = "datac";
defparam \PS[2] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y1_N3
maxii_lcell \PS[3] (
// Equation(s):
// PS[3] = DFFEAS(PS[3] $ (((PS[2] & (PS[1] & PS[0])))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(PS[3]),
	.datab(PS[2]),
	.datac(PS[1]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(PS[3]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \PS[3] .lut_mask = "6aaa";
defparam \PS[3] .operation_mode = "normal";
defparam \PS[3] .output_mode = "reg_only";
defparam \PS[3] .register_cascade_mode = "off";
defparam \PS[3] .sum_lutc_input = "datac";
defparam \PS[3] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y1_N5
maxii_lcell \Equal2~1 (
// Equation(s):
// \Equal2~1_combout  = (PS[3] & (PS[2] & (PS[1] & PS[0])))

	.clk(gnd),
	.dataa(PS[3]),
	.datab(PS[2]),
	.datac(PS[1]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Equal2~1_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Equal2~1 .lut_mask = "8000";
defparam \Equal2~1 .operation_mode = "normal";
defparam \Equal2~1 .output_mode = "comb_only";
defparam \Equal2~1 .register_cascade_mode = "off";
defparam \Equal2~1 .sum_lutc_input = "datac";
defparam \Equal2~1 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y3_N1
maxii_lcell \LS[0] (
// Equation(s):
// LS[0] = DFFEAS(((\Equal2~1_combout  $ (LS[0]))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\Equal2~1_combout ),
	.datad(LS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(LS[0]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \LS[0] .lut_mask = "0ff0";
defparam \LS[0] .operation_mode = "normal";
defparam \LS[0] .output_mode = "reg_only";
defparam \LS[0] .register_cascade_mode = "off";
defparam \LS[0] .sum_lutc_input = "datac";
defparam \LS[0] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y3_N4
maxii_lcell \LS[1] (
// Equation(s):
// LS[1] = DFFEAS(LS[1] $ ((LS[0])), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , )
// \LS[1]~3  = CARRY((LS[1] & (LS[0])))

	.clk(\C25M~combout ),
	.dataa(LS[1]),
	.datab(LS[0]),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal2~1_combout ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(LS[1]),
	.cout(\LS[1]~3 ),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \LS[1] .lut_mask = "6688";
defparam \LS[1] .operation_mode = "arithmetic";
defparam \LS[1] .output_mode = "reg_only";
defparam \LS[1] .register_cascade_mode = "off";
defparam \LS[1] .sum_lutc_input = "datac";
defparam \LS[1] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y3_N5
maxii_lcell \LS[2] (
// Equation(s):
// LS[2] = DFFEAS(LS[2] $ ((((\LS[1]~3 )))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , )
// \LS[2]~7  = CARRY(((!\LS[1]~3 )) # (!LS[2]))
// \LS[2]~7COUT1_28  = CARRY(((!\LS[1]~3 )) # (!LS[2]))

	.clk(\C25M~combout ),
	.dataa(LS[2]),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal2~1_combout ),
	.cin(\LS[1]~3 ),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(LS[2]),
	.cout(),
	.cout0(\LS[2]~7 ),
	.cout1(\LS[2]~7COUT1_28 ));
// synopsys translate_off
defparam \LS[2] .cin_used = "true";
defparam \LS[2] .lut_mask = "5a5f";
defparam \LS[2] .operation_mode = "arithmetic";
defparam \LS[2] .output_mode = "reg_only";
defparam \LS[2] .register_cascade_mode = "off";
defparam \LS[2] .sum_lutc_input = "cin";
defparam \LS[2] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y3_N6
maxii_lcell \LS[3] (
// Equation(s):
// LS[3] = DFFEAS(LS[3] $ ((((!(!\LS[1]~3  & \LS[2]~7 ) # (\LS[1]~3  & \LS[2]~7COUT1_28 ))))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , )
// \LS[3]~11  = CARRY((LS[3] & ((!\LS[2]~7 ))))
// \LS[3]~11COUT1_29  = CARRY((LS[3] & ((!\LS[2]~7COUT1_28 ))))

	.clk(\C25M~combout ),
	.dataa(LS[3]),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal2~1_combout ),
	.cin(\LS[1]~3 ),
	.cin0(\LS[2]~7 ),
	.cin1(\LS[2]~7COUT1_28 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(LS[3]),
	.cout(),
	.cout0(\LS[3]~11 ),
	.cout1(\LS[3]~11COUT1_29 ));
// synopsys translate_off
defparam \LS[3] .cin0_used = "true";
defparam \LS[3] .cin1_used = "true";
defparam \LS[3] .cin_used = "true";
defparam \LS[3] .lut_mask = "a50a";
defparam \LS[3] .operation_mode = "arithmetic";
defparam \LS[3] .output_mode = "reg_only";
defparam \LS[3] .register_cascade_mode = "off";
defparam \LS[3] .sum_lutc_input = "cin";
defparam \LS[3] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y3_N7
maxii_lcell \LS[4] (
// Equation(s):
// LS[4] = DFFEAS((LS[4] $ (((!\LS[1]~3  & \LS[3]~11 ) # (\LS[1]~3  & \LS[3]~11COUT1_29 )))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , )
// \LS[4]~13  = CARRY(((!\LS[3]~11 ) # (!LS[4])))
// \LS[4]~13COUT1_30  = CARRY(((!\LS[3]~11COUT1_29 ) # (!LS[4])))

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(LS[4]),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal2~1_combout ),
	.cin(\LS[1]~3 ),
	.cin0(\LS[3]~11 ),
	.cin1(\LS[3]~11COUT1_29 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(LS[4]),
	.cout(),
	.cout0(\LS[4]~13 ),
	.cout1(\LS[4]~13COUT1_30 ));
// synopsys translate_off
defparam \LS[4] .cin0_used = "true";
defparam \LS[4] .cin1_used = "true";
defparam \LS[4] .cin_used = "true";
defparam \LS[4] .lut_mask = "3c3f";
defparam \LS[4] .operation_mode = "arithmetic";
defparam \LS[4] .output_mode = "reg_only";
defparam \LS[4] .register_cascade_mode = "off";
defparam \LS[4] .sum_lutc_input = "cin";
defparam \LS[4] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y3_N8
maxii_lcell \LS[5] (
// Equation(s):
// LS[5] = DFFEAS(LS[5] $ ((((!(!\LS[1]~3  & \LS[4]~13 ) # (\LS[1]~3  & \LS[4]~13COUT1_30 ))))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , )
// \LS[5]~15  = CARRY((LS[5] & ((!\LS[4]~13 ))))
// \LS[5]~15COUT1_31  = CARRY((LS[5] & ((!\LS[4]~13COUT1_30 ))))

	.clk(\C25M~combout ),
	.dataa(LS[5]),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal2~1_combout ),
	.cin(\LS[1]~3 ),
	.cin0(\LS[4]~13 ),
	.cin1(\LS[4]~13COUT1_30 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(LS[5]),
	.cout(),
	.cout0(\LS[5]~15 ),
	.cout1(\LS[5]~15COUT1_31 ));
// synopsys translate_off
defparam \LS[5] .cin0_used = "true";
defparam \LS[5] .cin1_used = "true";
defparam \LS[5] .cin_used = "true";
defparam \LS[5] .lut_mask = "a50a";
defparam \LS[5] .operation_mode = "arithmetic";
defparam \LS[5] .output_mode = "reg_only";
defparam \LS[5] .register_cascade_mode = "off";
defparam \LS[5] .sum_lutc_input = "cin";
defparam \LS[5] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y3_N9
maxii_lcell \LS[6] (
// Equation(s):
// LS[6] = DFFEAS((LS[6] $ (((!\LS[1]~3  & \LS[5]~15 ) # (\LS[1]~3  & \LS[5]~15COUT1_31 )))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , )
// \LS[6]~17  = CARRY(((!\LS[5]~15COUT1_31 ) # (!LS[6])))

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(LS[6]),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal2~1_combout ),
	.cin(\LS[1]~3 ),
	.cin0(\LS[5]~15 ),
	.cin1(\LS[5]~15COUT1_31 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(LS[6]),
	.cout(\LS[6]~17 ),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \LS[6] .cin0_used = "true";
defparam \LS[6] .cin1_used = "true";
defparam \LS[6] .cin_used = "true";
defparam \LS[6] .lut_mask = "3c3f";
defparam \LS[6] .operation_mode = "arithmetic";
defparam \LS[6] .output_mode = "reg_only";
defparam \LS[6] .register_cascade_mode = "off";
defparam \LS[6] .sum_lutc_input = "cin";
defparam \LS[6] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y3_N0
maxii_lcell \LS[7] (
// Equation(s):
// LS[7] = DFFEAS((LS[7] $ ((!\LS[6]~17 ))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , )
// \LS[7]~19  = CARRY(((LS[7] & !\LS[6]~17 )))
// \LS[7]~19COUT1_32  = CARRY(((LS[7] & !\LS[6]~17 )))

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(LS[7]),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal2~1_combout ),
	.cin(\LS[6]~17 ),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(LS[7]),
	.cout(),
	.cout0(\LS[7]~19 ),
	.cout1(\LS[7]~19COUT1_32 ));
// synopsys translate_off
defparam \LS[7] .cin_used = "true";
defparam \LS[7] .lut_mask = "c30c";
defparam \LS[7] .operation_mode = "arithmetic";
defparam \LS[7] .output_mode = "reg_only";
defparam \LS[7] .register_cascade_mode = "off";
defparam \LS[7] .sum_lutc_input = "cin";
defparam \LS[7] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y3_N2
maxii_lcell \Equal3~0 (
// Equation(s):
// \Equal3~0_combout  = (LS[1] & (LS[7] & (LS[3] & LS[6])))

	.clk(gnd),
	.dataa(LS[1]),
	.datab(LS[7]),
	.datac(LS[3]),
	.datad(LS[6]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Equal3~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Equal3~0 .lut_mask = "8000";
defparam \Equal3~0 .operation_mode = "normal";
defparam \Equal3~0 .output_mode = "comb_only";
defparam \Equal3~0 .register_cascade_mode = "off";
defparam \Equal3~0 .sum_lutc_input = "datac";
defparam \Equal3~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y3_N1
maxii_lcell \LS[8] (
// Equation(s):
// LS[8] = DFFEAS((LS[8] $ (((!\LS[6]~17  & \LS[7]~19 ) # (\LS[6]~17  & \LS[7]~19COUT1_32 )))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , )
// \LS[8]~21  = CARRY(((!\LS[7]~19 ) # (!LS[8])))
// \LS[8]~21COUT1_33  = CARRY(((!\LS[7]~19COUT1_32 ) # (!LS[8])))

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(LS[8]),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal2~1_combout ),
	.cin(\LS[6]~17 ),
	.cin0(\LS[7]~19 ),
	.cin1(\LS[7]~19COUT1_32 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(LS[8]),
	.cout(),
	.cout0(\LS[8]~21 ),
	.cout1(\LS[8]~21COUT1_33 ));
// synopsys translate_off
defparam \LS[8] .cin0_used = "true";
defparam \LS[8] .cin1_used = "true";
defparam \LS[8] .cin_used = "true";
defparam \LS[8] .lut_mask = "3c3f";
defparam \LS[8] .operation_mode = "arithmetic";
defparam \LS[8] .output_mode = "reg_only";
defparam \LS[8] .register_cascade_mode = "off";
defparam \LS[8] .sum_lutc_input = "cin";
defparam \LS[8] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y3_N2
maxii_lcell \LS[9] (
// Equation(s):
// LS[9] = DFFEAS((LS[9] $ ((!(!\LS[6]~17  & \LS[8]~21 ) # (\LS[6]~17  & \LS[8]~21COUT1_33 )))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , )
// \LS[9]~23  = CARRY(((LS[9] & !\LS[8]~21 )))
// \LS[9]~23COUT1_34  = CARRY(((LS[9] & !\LS[8]~21COUT1_33 )))

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(LS[9]),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal2~1_combout ),
	.cin(\LS[6]~17 ),
	.cin0(\LS[8]~21 ),
	.cin1(\LS[8]~21COUT1_33 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(LS[9]),
	.cout(),
	.cout0(\LS[9]~23 ),
	.cout1(\LS[9]~23COUT1_34 ));
// synopsys translate_off
defparam \LS[9] .cin0_used = "true";
defparam \LS[9] .cin1_used = "true";
defparam \LS[9] .cin_used = "true";
defparam \LS[9] .lut_mask = "c30c";
defparam \LS[9] .operation_mode = "arithmetic";
defparam \LS[9] .output_mode = "reg_only";
defparam \LS[9] .register_cascade_mode = "off";
defparam \LS[9] .sum_lutc_input = "cin";
defparam \LS[9] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y3_N3
maxii_lcell \LS[10] (
// Equation(s):
// LS[10] = DFFEAS(LS[10] $ (((((!\LS[6]~17  & \LS[9]~23 ) # (\LS[6]~17  & \LS[9]~23COUT1_34 ))))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , )
// \LS[10]~1  = CARRY(((!\LS[9]~23 )) # (!LS[10]))
// \LS[10]~1COUT1_35  = CARRY(((!\LS[9]~23COUT1_34 )) # (!LS[10]))

	.clk(\C25M~combout ),
	.dataa(LS[10]),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal2~1_combout ),
	.cin(\LS[6]~17 ),
	.cin0(\LS[9]~23 ),
	.cin1(\LS[9]~23COUT1_34 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(LS[10]),
	.cout(),
	.cout0(\LS[10]~1 ),
	.cout1(\LS[10]~1COUT1_35 ));
// synopsys translate_off
defparam \LS[10] .cin0_used = "true";
defparam \LS[10] .cin1_used = "true";
defparam \LS[10] .cin_used = "true";
defparam \LS[10] .lut_mask = "5a5f";
defparam \LS[10] .operation_mode = "arithmetic";
defparam \LS[10] .output_mode = "reg_only";
defparam \LS[10] .register_cascade_mode = "off";
defparam \LS[10] .sum_lutc_input = "cin";
defparam \LS[10] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y3_N4
maxii_lcell \LS[11] (
// Equation(s):
// LS[11] = DFFEAS(LS[11] $ ((((!(!\LS[6]~17  & \LS[10]~1 ) # (\LS[6]~17  & \LS[10]~1COUT1_35 ))))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , )
// \LS[11]~5  = CARRY((LS[11] & ((!\LS[10]~1COUT1_35 ))))

	.clk(\C25M~combout ),
	.dataa(LS[11]),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal2~1_combout ),
	.cin(\LS[6]~17 ),
	.cin0(\LS[10]~1 ),
	.cin1(\LS[10]~1COUT1_35 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(LS[11]),
	.cout(\LS[11]~5 ),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \LS[11] .cin0_used = "true";
defparam \LS[11] .cin1_used = "true";
defparam \LS[11] .cin_used = "true";
defparam \LS[11] .lut_mask = "a50a";
defparam \LS[11] .operation_mode = "arithmetic";
defparam \LS[11] .output_mode = "reg_only";
defparam \LS[11] .register_cascade_mode = "off";
defparam \LS[11] .sum_lutc_input = "cin";
defparam \LS[11] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y3_N5
maxii_lcell \LS[12] (
// Equation(s):
// LS[12] = DFFEAS(LS[12] $ ((((\LS[11]~5 )))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , )
// \LS[12]~9  = CARRY(((!\LS[11]~5 )) # (!LS[12]))
// \LS[12]~9COUT1_36  = CARRY(((!\LS[11]~5 )) # (!LS[12]))

	.clk(\C25M~combout ),
	.dataa(LS[12]),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal2~1_combout ),
	.cin(\LS[11]~5 ),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(LS[12]),
	.cout(),
	.cout0(\LS[12]~9 ),
	.cout1(\LS[12]~9COUT1_36 ));
// synopsys translate_off
defparam \LS[12] .cin_used = "true";
defparam \LS[12] .lut_mask = "5a5f";
defparam \LS[12] .operation_mode = "arithmetic";
defparam \LS[12] .output_mode = "reg_only";
defparam \LS[12] .register_cascade_mode = "off";
defparam \LS[12] .sum_lutc_input = "cin";
defparam \LS[12] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y3_N9
maxii_lcell \Equal3~1 (
// Equation(s):
// \Equal3~1_combout  = (LS[10] & (LS[8] & (LS[11] & LS[9])))

	.clk(gnd),
	.dataa(LS[10]),
	.datab(LS[8]),
	.datac(LS[11]),
	.datad(LS[9]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Equal3~1_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Equal3~1 .lut_mask = "8000";
defparam \Equal3~1 .operation_mode = "normal";
defparam \Equal3~1 .output_mode = "comb_only";
defparam \Equal3~1 .register_cascade_mode = "off";
defparam \Equal3~1 .sum_lutc_input = "datac";
defparam \Equal3~1 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y3_N8
maxii_lcell \Equal3~2 (
// Equation(s):
// \Equal3~2_combout  = ((\Equal3~0_combout  & (LS[12] & \Equal3~1_combout )))

	.clk(gnd),
	.dataa(vcc),
	.datab(\Equal3~0_combout ),
	.datac(LS[12]),
	.datad(\Equal3~1_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Equal3~2_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Equal3~2 .lut_mask = "c000";
defparam \Equal3~2 .operation_mode = "normal";
defparam \Equal3~2 .output_mode = "comb_only";
defparam \Equal3~2 .register_cascade_mode = "off";
defparam \Equal3~2 .sum_lutc_input = "datac";
defparam \Equal3~2 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y3_N3
maxii_lcell \Equal5~0 (
// Equation(s):
// \Equal5~0_combout  = (LS[5] & (((LS[4] & \Equal3~2_combout ))))

	.clk(gnd),
	.dataa(LS[5]),
	.datab(vcc),
	.datac(LS[4]),
	.datad(\Equal3~2_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Equal5~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Equal5~0 .lut_mask = "a000";
defparam \Equal5~0 .operation_mode = "normal";
defparam \Equal5~0 .output_mode = "comb_only";
defparam \Equal5~0 .register_cascade_mode = "off";
defparam \Equal5~0 .sum_lutc_input = "datac";
defparam \Equal5~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y2_N6
maxii_lcell \Equal6~0 (
// Equation(s):
// \Equal6~0_combout  = (LS[0] & (\Equal5~0_combout  & (LS[2])))

	.clk(gnd),
	.dataa(LS[0]),
	.datab(\Equal5~0_combout ),
	.datac(LS[2]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Equal6~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Equal6~0 .lut_mask = "8080";
defparam \Equal6~0 .operation_mode = "normal";
defparam \Equal6~0 .output_mode = "comb_only";
defparam \Equal6~0 .register_cascade_mode = "off";
defparam \Equal6~0 .sum_lutc_input = "datac";
defparam \Equal6~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y3_N6
maxii_lcell \LS[13] (
// Equation(s):
// LS[13] = DFFEAS((((!\LS[11]~5  & \LS[12]~9 ) # (\LS[11]~5  & \LS[12]~9COUT1_36 ) $ (!LS[13]))), GLOBAL(\C25M~combout ), VCC, , \Equal2~1_combout , , , , )

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(LS[13]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal2~1_combout ),
	.cin(\LS[11]~5 ),
	.cin0(\LS[12]~9 ),
	.cin1(\LS[12]~9COUT1_36 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(LS[13]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \LS[13] .cin0_used = "true";
defparam \LS[13] .cin1_used = "true";
defparam \LS[13] .cin_used = "true";
defparam \LS[13] .lut_mask = "f00f";
defparam \LS[13] .operation_mode = "normal";
defparam \LS[13] .output_mode = "reg_only";
defparam \LS[13] .register_cascade_mode = "off";
defparam \LS[13] .sum_lutc_input = "cin";
defparam \LS[13] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y2_N9
maxii_lcell \IS.111 (
// Equation(s):
// \IS.111~regout  = DFFEAS((\IS.111~regout ) # ((\Equal2~1_combout  & (\Equal6~0_combout  & LS[13]))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(\Equal2~1_combout ),
	.datab(\IS.111~regout ),
	.datac(\Equal6~0_combout ),
	.datad(LS[13]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\IS.111~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \IS.111 .lut_mask = "eccc";
defparam \IS.111 .operation_mode = "normal";
defparam \IS.111 .output_mode = "reg_only";
defparam \IS.111 .register_cascade_mode = "off";
defparam \IS.111 .sum_lutc_input = "datac";
defparam \IS.111 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y1_N8
maxii_lcell \nRESout~reg0 (
// Equation(s):
// \nRESout~reg0_regout  = DFFEAS((((\IS.111~regout ) # (\nRESout~reg0_regout ))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\IS.111~regout ),
	.datad(\nRESout~reg0_regout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\nRESout~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \nRESout~reg0 .lut_mask = "fff0";
defparam \nRESout~reg0 .operation_mode = "normal";
defparam \nRESout~reg0 .output_mode = "reg_only";
defparam \nRESout~reg0 .register_cascade_mode = "off";
defparam \nRESout~reg0 .sum_lutc_input = "datac";
defparam \nRESout~reg0 .synch_mode = "off";
// synopsys translate_on

// Location: PIN_49,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \INTin~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\INTin~combout ),
	.padio(INTin));
// synopsys translate_off
defparam \INTin~I .operation_mode = "input";
// synopsys translate_on

// Location: PIN_48,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \DMAin~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\DMAin~combout ),
	.padio(DMAin));
// synopsys translate_off
defparam \DMAin~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X2_Y2_N4
maxii_lcell \IS~17 (
// Equation(s):
// \IS~17_combout  = (((\IS.111~regout ) # (!\Equal2~1_combout )))

	.clk(gnd),
	.dataa(vcc),
	.datab(vcc),
	.datac(\Equal2~1_combout ),
	.datad(\IS.111~regout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\IS~17_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \IS~17 .lut_mask = "ff0f";
defparam \IS~17 .operation_mode = "normal";
defparam \IS~17 .output_mode = "comb_only";
defparam \IS~17 .register_cascade_mode = "off";
defparam \IS~17 .sum_lutc_input = "datac";
defparam \IS~17 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y2_N2
maxii_lcell \IS~18 (
// Equation(s):
// \IS~18_combout  = ((LS[2] & (!LS[0])) # (!LS[2] & ((LS[0]) # (LS[13])))) # (!\Equal5~0_combout )

	.clk(gnd),
	.dataa(LS[2]),
	.datab(\Equal5~0_combout ),
	.datac(LS[0]),
	.datad(LS[13]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\IS~18_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \IS~18 .lut_mask = "7f7b";
defparam \IS~18 .operation_mode = "normal";
defparam \IS~18 .output_mode = "comb_only";
defparam \IS~18 .register_cascade_mode = "off";
defparam \IS~18 .sum_lutc_input = "datac";
defparam \IS~18 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y3_N0
maxii_lcell \Equal3~3 (
// Equation(s):
// \Equal3~3_combout  = (LS[2] & (!LS[4] & (!LS[13] & !LS[5])))

	.clk(gnd),
	.dataa(LS[2]),
	.datab(LS[4]),
	.datac(LS[13]),
	.datad(LS[5]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Equal3~3_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Equal3~3 .lut_mask = "0002";
defparam \Equal3~3 .operation_mode = "normal";
defparam \Equal3~3 .output_mode = "comb_only";
defparam \Equal3~3 .register_cascade_mode = "off";
defparam \Equal3~3 .sum_lutc_input = "datac";
defparam \Equal3~3 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y2_N0
maxii_lcell \IS.100 (
// Equation(s):
// \Equal4~0  = (LS[0] & (((\Equal3~3_combout  & \Equal3~2_combout ))))
// \IS.100~regout  = DFFEAS(\Equal4~0 , GLOBAL(\C25M~combout ), VCC, , \IS~19_combout , , , , )

	.clk(\C25M~combout ),
	.dataa(LS[0]),
	.datab(vcc),
	.datac(\Equal3~3_combout ),
	.datad(\Equal3~2_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\IS~19_combout ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Equal4~0 ),
	.regout(\IS.100~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \IS.100 .lut_mask = "a000";
defparam \IS.100 .operation_mode = "normal";
defparam \IS.100 .output_mode = "reg_and_comb";
defparam \IS.100 .register_cascade_mode = "off";
defparam \IS.100 .sum_lutc_input = "datac";
defparam \IS.100 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y2_N3
maxii_lcell \IS.001 (
// Equation(s):
// \Equal3~4  = (!LS[0] & (((\Equal3~3_combout  & \Equal3~2_combout ))))
// \IS.001~regout  = DFFEAS(\Equal3~4 , GLOBAL(\C25M~combout ), VCC, , \IS~19_combout , , , , )

	.clk(\C25M~combout ),
	.dataa(LS[0]),
	.datab(vcc),
	.datac(\Equal3~3_combout ),
	.datad(\Equal3~2_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\IS~19_combout ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Equal3~4 ),
	.regout(\IS.001~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \IS.001 .lut_mask = "5000";
defparam \IS.001 .operation_mode = "normal";
defparam \IS.001 .output_mode = "reg_and_comb";
defparam \IS.001 .register_cascade_mode = "off";
defparam \IS.001 .sum_lutc_input = "datac";
defparam \IS.001 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y2_N7
maxii_lcell \IS~19 (
// Equation(s):
// \IS~19_combout  = (!\IS~17_combout  & (((\Equal4~0 ) # (\Equal3~4 )) # (!\IS~18_combout )))

	.clk(gnd),
	.dataa(\IS~17_combout ),
	.datab(\IS~18_combout ),
	.datac(\Equal4~0 ),
	.datad(\Equal3~4 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\IS~19_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \IS~19 .lut_mask = "5551";
defparam \IS~19 .operation_mode = "normal";
defparam \IS~19 .output_mode = "comb_only";
defparam \IS~19 .register_cascade_mode = "off";
defparam \IS~19 .sum_lutc_input = "datac";
defparam \IS~19 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y2_N5
maxii_lcell \IS.110 (
// Equation(s):
// \IS.110~regout  = DFFEAS((LS[2] & (\Equal5~0_combout  & (LS[0] & !LS[13]))), GLOBAL(\C25M~combout ), VCC, , \IS~19_combout , , , , )

	.clk(\C25M~combout ),
	.dataa(LS[2]),
	.datab(\Equal5~0_combout ),
	.datac(LS[0]),
	.datad(LS[13]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\IS~19_combout ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\IS.110~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \IS.110 .lut_mask = "0080";
defparam \IS.110 .operation_mode = "normal";
defparam \IS.110 .output_mode = "reg_only";
defparam \IS.110 .register_cascade_mode = "off";
defparam \IS.110 .sum_lutc_input = "datac";
defparam \IS.110 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y2_N3
maxii_lcell \SA[1]~3 (
// Equation(s):
// \SA[1]~3_combout  = (((!PS[1] & \IS.110~regout )) # (!PS[0]))

	.clk(gnd),
	.dataa(vcc),
	.datab(PS[1]),
	.datac(\IS.110~regout ),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\SA[1]~3_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[1]~3 .lut_mask = "30ff";
defparam \SA[1]~3 .operation_mode = "normal";
defparam \SA[1]~3 .output_mode = "comb_only";
defparam \SA[1]~3 .register_cascade_mode = "off";
defparam \SA[1]~3 .sum_lutc_input = "datac";
defparam \SA[1]~3 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y3_N7
maxii_lcell \Mux22~0 (
// Equation(s):
// \Mux22~0_combout  = ((PS[0] & (LS[12])))

	.clk(gnd),
	.dataa(vcc),
	.datab(PS[0]),
	.datac(LS[12]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux22~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux22~0 .lut_mask = "c0c0";
defparam \Mux22~0 .operation_mode = "normal";
defparam \Mux22~0 .output_mode = "comb_only";
defparam \Mux22~0 .register_cascade_mode = "off";
defparam \Mux22~0 .sum_lutc_input = "datac";
defparam \Mux22~0 .synch_mode = "off";
// synopsys translate_on

// Location: PIN_4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \RA[3]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\RA~combout [3]),
	.padio(RA[3]));
// synopsys translate_off
defparam \RA[3]~I .operation_mode = "input";
// synopsys translate_on

// Location: PIN_98,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \RA[1]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\RA~combout [1]),
	.padio(RA[1]));
// synopsys translate_off
defparam \RA[1]~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X4_Y3_N4
maxii_lcell \RAr[1] (
// Equation(s):
// \RAMRegSpecSEL~0  = (RAr[0] & (((RAr[1]))))
// RAr[1] = DFFEAS(\RAMRegSpecSEL~0 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [1], , , VCC)

	.clk(\PHI0~combout ),
	.dataa(RAr[0]),
	.datab(vcc),
	.datac(\RA~combout [1]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\RAMRegSpecSEL~0 ),
	.regout(RAr[1]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RAr[1] .lut_mask = "a0a0";
defparam \RAr[1] .operation_mode = "normal";
defparam \RAr[1] .output_mode = "reg_and_comb";
defparam \RAr[1] .register_cascade_mode = "off";
defparam \RAr[1] .sum_lutc_input = "qfbk";
defparam \RAr[1] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X3_Y2_N3
maxii_lcell \SA[1]~2 (
// Equation(s):
// \SA[1]~2_combout  = (PS[1]) # (((\IS.110~regout ) # (!PS[0])))

	.clk(gnd),
	.dataa(PS[1]),
	.datab(vcc),
	.datac(\IS.110~regout ),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\SA[1]~2_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[1]~2 .lut_mask = "faff";
defparam \SA[1]~2 .operation_mode = "normal";
defparam \SA[1]~2 .output_mode = "comb_only";
defparam \SA[1]~2 .register_cascade_mode = "off";
defparam \SA[1]~2 .sum_lutc_input = "datac";
defparam \SA[1]~2 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y3_N8
maxii_lcell \Mux24~0 (
// Equation(s):
// \Mux24~0_combout  = ((LS[10] & ((PS[0]))))

	.clk(gnd),
	.dataa(vcc),
	.datab(LS[10]),
	.datac(vcc),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux24~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux24~0 .lut_mask = "cc00";
defparam \Mux24~0 .operation_mode = "normal";
defparam \Mux24~0 .output_mode = "comb_only";
defparam \Mux24~0 .register_cascade_mode = "off";
defparam \Mux24~0 .sum_lutc_input = "datac";
defparam \Mux24~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y3_N3
maxii_lcell \Mux24~1 (
// Equation(s):
// \Mux24~1_combout  = (\SA[1]~4_combout  & (((RAr[1] & \SA[1]~3_combout )))) # (!\SA[1]~4_combout  & ((\Mux24~0_combout ) # ((!\SA[1]~3_combout ))))

	.clk(gnd),
	.dataa(\Mux24~0_combout ),
	.datab(\SA[1]~4_combout ),
	.datac(RAr[1]),
	.datad(\SA[1]~3_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux24~1_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux24~1 .lut_mask = "e233";
defparam \Mux24~1 .operation_mode = "normal";
defparam \Mux24~1 .output_mode = "comb_only";
defparam \Mux24~1 .register_cascade_mode = "off";
defparam \Mux24~1 .sum_lutc_input = "datac";
defparam \Mux24~1 .synch_mode = "off";
// synopsys translate_on

// Location: PIN_14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \RA[10]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\RA~combout [10]),
	.padio(RA[10]));
// synopsys translate_off
defparam \RA[10]~I .operation_mode = "input";
// synopsys translate_on

// Location: PIN_44,	 I/O Standard: 3.3V Schmitt Trigger Input,	 Current Strength: Default
maxii_io \nRES~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\nRES~combout ),
	.padio(nRES));
// synopsys translate_off
defparam \nRES~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X3_Y1_N4
maxii_lcell \nRESf[0] (
// Equation(s):
// nRESf[0] = DFFEAS(GND, GLOBAL(\C25M~combout ), VCC, , , \nRES~combout , , , VCC)

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\nRES~combout ),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(nRESf[0]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \nRESf[0] .lut_mask = "0000";
defparam \nRESf[0] .operation_mode = "normal";
defparam \nRESf[0] .output_mode = "reg_only";
defparam \nRESf[0] .register_cascade_mode = "off";
defparam \nRESf[0] .sum_lutc_input = "datac";
defparam \nRESf[0] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X3_Y1_N6
maxii_lcell \nRESf[1] (
// Equation(s):
// nRESf[1] = DFFEAS(GND, GLOBAL(\C25M~combout ), VCC, , , nRESf[0], , , VCC)

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(nRESf[0]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(nRESf[1]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \nRESf[1] .lut_mask = "0000";
defparam \nRESf[1] .operation_mode = "normal";
defparam \nRESf[1] .output_mode = "reg_only";
defparam \nRESf[1] .register_cascade_mode = "off";
defparam \nRESf[1] .sum_lutc_input = "datac";
defparam \nRESf[1] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X3_Y1_N5
maxii_lcell \nRESf[2] (
// Equation(s):
// nRESf[2] = DFFEAS(GND, GLOBAL(\C25M~combout ), VCC, , , nRESf[1], , , VCC)

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(nRESf[1]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(nRESf[2]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \nRESf[2] .lut_mask = "0000";
defparam \nRESf[2] .operation_mode = "normal";
defparam \nRESf[2] .output_mode = "reg_only";
defparam \nRESf[2] .register_cascade_mode = "off";
defparam \nRESf[2] .sum_lutc_input = "datac";
defparam \nRESf[2] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X3_Y1_N9
maxii_lcell \nRESf[3] (
// Equation(s):
// nRESf[3] = DFFEAS(GND, GLOBAL(\C25M~combout ), VCC, , , nRESf[2], , , VCC)

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(nRESf[2]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(nRESf[3]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \nRESf[3] .lut_mask = "0000";
defparam \nRESf[3] .operation_mode = "normal";
defparam \nRESf[3] .output_mode = "reg_only";
defparam \nRESf[3] .register_cascade_mode = "off";
defparam \nRESf[3] .sum_lutc_input = "datac";
defparam \nRESf[3] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X3_Y1_N7
maxii_lcell nRESr(
// Equation(s):
// \nRESr~regout  = DFFEAS((nRESf[0]) # ((nRESf[3]) # ((nRESf[2]) # (nRESf[1]))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(nRESf[0]),
	.datab(nRESf[3]),
	.datac(nRESf[2]),
	.datad(nRESf[1]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\nRESr~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam nRESr.lut_mask = "fffe";
defparam nRESr.operation_mode = "normal";
defparam nRESr.output_mode = "reg_only";
defparam nRESr.register_cascade_mode = "off";
defparam nRESr.sum_lutc_input = "datac";
defparam nRESr.synch_mode = "off";
// synopsys translate_on

// Location: PIN_40,	 I/O Standard: 3.3V Schmitt Trigger Input,	 Current Strength: Default
maxii_io \nDEVSEL~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\nDEVSEL~combout ),
	.padio(nDEVSEL));
// synopsys translate_off
defparam \nDEVSEL~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X5_Y1_N3
maxii_lcell \nRCS~0 (
// Equation(s):
// \nRCS~0_combout  = (((!\nDEVSEL~combout  & \IS.111~regout )))

	.clk(gnd),
	.dataa(vcc),
	.datab(vcc),
	.datac(\nDEVSEL~combout ),
	.datad(\IS.111~regout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\nRCS~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \nRCS~0 .lut_mask = "0f00";
defparam \nRCS~0 .operation_mode = "normal";
defparam \nRCS~0 .output_mode = "comb_only";
defparam \nRCS~0 .register_cascade_mode = "off";
defparam \nRCS~0 .sum_lutc_input = "datac";
defparam \nRCS~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y1_N2
maxii_lcell nWEr(
// Equation(s):
// \nRCS~1  = (\IS.110~regout ) # ((\nRCS~0_combout  & (\RAMSpecSEL~1_combout  & !nWEr)))
// \nWEr~regout  = DFFEAS(\nRCS~1 , GLOBAL(\PHI0~combout ), VCC, , , \nWE~combout , , , VCC)

	.clk(\PHI0~combout ),
	.dataa(\nRCS~0_combout ),
	.datab(\RAMSpecSEL~1_combout ),
	.datac(\nWE~combout ),
	.datad(\IS.110~regout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\nRCS~1 ),
	.regout(\nWEr~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam nWEr.lut_mask = "ff08";
defparam nWEr.operation_mode = "normal";
defparam nWEr.output_mode = "reg_and_comb";
defparam nWEr.register_cascade_mode = "off";
defparam nWEr.sum_lutc_input = "qfbk";
defparam nWEr.synch_mode = "on";
// synopsys translate_on

// Location: LC_X2_Y1_N7
maxii_lcell \Equal19~0 (
// Equation(s):
// \Equal19~0_combout  = (PS[3] & (!PS[2] & (!PS[1] & !PS[0])))

	.clk(gnd),
	.dataa(PS[3]),
	.datab(PS[2]),
	.datac(PS[1]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Equal19~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Equal19~0 .lut_mask = "0002";
defparam \Equal19~0 .operation_mode = "normal";
defparam \Equal19~0 .output_mode = "comb_only";
defparam \Equal19~0 .register_cascade_mode = "off";
defparam \Equal19~0 .sum_lutc_input = "datac";
defparam \Equal19~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y1_N5
maxii_lcell \always9~1 (
// Equation(s):
// \always9~1_combout  = (!\nWEr~regout  & (!\nDEVSEL~combout  & (\Equal19~0_combout  & \always9~0_combout )))

	.clk(gnd),
	.dataa(\nWEr~regout ),
	.datab(\nDEVSEL~combout ),
	.datac(\Equal19~0_combout ),
	.datad(\always9~0_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\always9~1_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \always9~1 .lut_mask = "1000";
defparam \always9~1 .operation_mode = "normal";
defparam \always9~1 .output_mode = "comb_only";
defparam \always9~1 .register_cascade_mode = "off";
defparam \always9~1 .sum_lutc_input = "datac";
defparam \always9~1 .synch_mode = "off";
// synopsys translate_on

// Location: PIN_97,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \RA[2]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\RA~combout [2]),
	.padio(RA[2]));
// synopsys translate_off
defparam \RA[2]~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X4_Y3_N0
maxii_lcell \RAr[2] (
// Equation(s):
// \RAMRegSpecSEL~1  = (!RAr[3] & (((!RAr[2]))))
// RAr[2] = DFFEAS(\RAMRegSpecSEL~1 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [2], , , VCC)

	.clk(\PHI0~combout ),
	.dataa(RAr[3]),
	.datab(vcc),
	.datac(\RA~combout [2]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\RAMRegSpecSEL~1 ),
	.regout(RAr[2]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RAr[2] .lut_mask = "0505";
defparam \RAr[2] .operation_mode = "normal";
defparam \RAr[2] .output_mode = "reg_and_comb";
defparam \RAr[2] .register_cascade_mode = "off";
defparam \RAr[2] .sum_lutc_input = "qfbk";
defparam \RAr[2] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X7_Y3_N7
maxii_lcell \always9~3 (
// Equation(s):
// \always9~3_combout  = (\always9~1_combout  & (RAr[0] & (!RAr[1] & \RAMRegSpecSEL~1 )))

	.clk(gnd),
	.dataa(\always9~1_combout ),
	.datab(RAr[0]),
	.datac(RAr[1]),
	.datad(\RAMRegSpecSEL~1 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\always9~3_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \always9~3 .lut_mask = "0800";
defparam \always9~3 .operation_mode = "normal";
defparam \always9~3 .output_mode = "comb_only";
defparam \always9~3 .register_cascade_mode = "off";
defparam \always9~3 .sum_lutc_input = "datac";
defparam \always9~3 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y3_N9
maxii_lcell \always9~4 (
// Equation(s):
// \always9~4_combout  = (\RAMRegSpecSEL~1  & (!RAr[1] & (\always9~1_combout  & !RAr[0])))

	.clk(gnd),
	.dataa(\RAMRegSpecSEL~1 ),
	.datab(RAr[1]),
	.datac(\always9~1_combout ),
	.datad(RAr[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\always9~4_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \always9~4 .lut_mask = "0020";
defparam \always9~4 .operation_mode = "normal";
defparam \always9~4 .output_mode = "comb_only";
defparam \always9~4 .register_cascade_mode = "off";
defparam \always9~4 .sum_lutc_input = "datac";
defparam \always9~4 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y1_N1
maxii_lcell \always9~5 (
// Equation(s):
// \always9~5_combout  = (!\nDEVSEL~combout  & (((\Equal19~0_combout ))))

	.clk(gnd),
	.dataa(\nDEVSEL~combout ),
	.datab(vcc),
	.datac(\Equal19~0_combout ),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\always9~5_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \always9~5 .lut_mask = "5050";
defparam \always9~5 .operation_mode = "normal";
defparam \always9~5 .output_mode = "comb_only";
defparam \always9~5 .register_cascade_mode = "off";
defparam \always9~5 .sum_lutc_input = "datac";
defparam \always9~5 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y3_N6
maxii_lcell AddrIncL(
// Equation(s):
// \AddrIncL~regout  = DFFEAS((\always9~5_combout  & (\always9~0_combout  & (\RAMRegSpecSEL~0  & \RAMRegSpecSEL~1 ))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , , , , )

	.clk(\C25M~combout ),
	.dataa(\always9~5_combout ),
	.datab(\always9~0_combout ),
	.datac(\RAMRegSpecSEL~0 ),
	.datad(\RAMRegSpecSEL~1 ),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\AddrIncL~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam AddrIncL.lut_mask = "8000";
defparam AddrIncL.operation_mode = "normal";
defparam AddrIncL.output_mode = "reg_only";
defparam AddrIncL.register_cascade_mode = "off";
defparam AddrIncL.sum_lutc_input = "datac";
defparam AddrIncL.synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y3_N0
maxii_lcell \Addr[0] (
// Equation(s):
// Addr[0] = DFFEAS(\AddrIncL~regout  $ ((Addr[0])), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[0]~0 , , , \always9~4_combout )
// \Addr[0]~47  = CARRY((\AddrIncL~regout  & (Addr[0])))
// \Addr[0]~47COUT1_61  = CARRY((\AddrIncL~regout  & (Addr[0])))

	.clk(\C25M~combout ),
	.dataa(\AddrIncL~regout ),
	.datab(Addr[0]),
	.datac(\RD[0]~0 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~4_combout ),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[0]),
	.cout(),
	.cout0(\Addr[0]~47 ),
	.cout1(\Addr[0]~47COUT1_61 ));
// synopsys translate_off
defparam \Addr[0] .lut_mask = "6688";
defparam \Addr[0] .operation_mode = "arithmetic";
defparam \Addr[0] .output_mode = "reg_only";
defparam \Addr[0] .register_cascade_mode = "off";
defparam \Addr[0] .sum_lutc_input = "datac";
defparam \Addr[0] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X6_Y3_N1
maxii_lcell \Addr[1] (
// Equation(s):
// Addr[1] = DFFEAS((Addr[1] $ ((\Addr[0]~47 ))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[1]~1 , , , \always9~4_combout )
// \Addr[1]~5  = CARRY(((!\Addr[0]~47 ) # (!Addr[1])))
// \Addr[1]~5COUT1_62  = CARRY(((!\Addr[0]~47COUT1_61 ) # (!Addr[1])))

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(Addr[1]),
	.datac(\RD[1]~1 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~4_combout ),
	.ena(vcc),
	.cin(gnd),
	.cin0(\Addr[0]~47 ),
	.cin1(\Addr[0]~47COUT1_61 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[1]),
	.cout(),
	.cout0(\Addr[1]~5 ),
	.cout1(\Addr[1]~5COUT1_62 ));
// synopsys translate_off
defparam \Addr[1] .cin0_used = "true";
defparam \Addr[1] .cin1_used = "true";
defparam \Addr[1] .lut_mask = "3c3f";
defparam \Addr[1] .operation_mode = "arithmetic";
defparam \Addr[1] .output_mode = "reg_only";
defparam \Addr[1] .register_cascade_mode = "off";
defparam \Addr[1] .sum_lutc_input = "cin";
defparam \Addr[1] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X6_Y3_N2
maxii_lcell \Addr[2] (
// Equation(s):
// Addr[2] = DFFEAS((Addr[2] $ ((!\Addr[1]~5 ))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[2]~2 , , , \always9~4_combout )
// \Addr[2]~9  = CARRY(((Addr[2] & !\Addr[1]~5 )))
// \Addr[2]~9COUT1_63  = CARRY(((Addr[2] & !\Addr[1]~5COUT1_62 )))

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(Addr[2]),
	.datac(\RD[2]~2 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~4_combout ),
	.ena(vcc),
	.cin(gnd),
	.cin0(\Addr[1]~5 ),
	.cin1(\Addr[1]~5COUT1_62 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[2]),
	.cout(),
	.cout0(\Addr[2]~9 ),
	.cout1(\Addr[2]~9COUT1_63 ));
// synopsys translate_off
defparam \Addr[2] .cin0_used = "true";
defparam \Addr[2] .cin1_used = "true";
defparam \Addr[2] .lut_mask = "c30c";
defparam \Addr[2] .operation_mode = "arithmetic";
defparam \Addr[2] .output_mode = "reg_only";
defparam \Addr[2] .register_cascade_mode = "off";
defparam \Addr[2] .sum_lutc_input = "cin";
defparam \Addr[2] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X6_Y3_N3
maxii_lcell \Addr[3] (
// Equation(s):
// Addr[3] = DFFEAS(Addr[3] $ ((((\Addr[2]~9 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[3]~3 , , , \always9~4_combout )
// \Addr[3]~13  = CARRY(((!\Addr[2]~9 )) # (!Addr[3]))
// \Addr[3]~13COUT1_64  = CARRY(((!\Addr[2]~9COUT1_63 )) # (!Addr[3]))

	.clk(\C25M~combout ),
	.dataa(Addr[3]),
	.datab(vcc),
	.datac(\RD[3]~3 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~4_combout ),
	.ena(vcc),
	.cin(gnd),
	.cin0(\Addr[2]~9 ),
	.cin1(\Addr[2]~9COUT1_63 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[3]),
	.cout(),
	.cout0(\Addr[3]~13 ),
	.cout1(\Addr[3]~13COUT1_64 ));
// synopsys translate_off
defparam \Addr[3] .cin0_used = "true";
defparam \Addr[3] .cin1_used = "true";
defparam \Addr[3] .lut_mask = "5a5f";
defparam \Addr[3] .operation_mode = "arithmetic";
defparam \Addr[3] .output_mode = "reg_only";
defparam \Addr[3] .register_cascade_mode = "off";
defparam \Addr[3] .sum_lutc_input = "cin";
defparam \Addr[3] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X6_Y3_N4
maxii_lcell \Addr[4] (
// Equation(s):
// Addr[4] = DFFEAS(Addr[4] $ ((((!\Addr[3]~13 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[4]~4 , , , \always9~4_combout )
// \Addr[4]~17  = CARRY((Addr[4] & ((!\Addr[3]~13COUT1_64 ))))

	.clk(\C25M~combout ),
	.dataa(Addr[4]),
	.datab(vcc),
	.datac(\RD[4]~4 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~4_combout ),
	.ena(vcc),
	.cin(gnd),
	.cin0(\Addr[3]~13 ),
	.cin1(\Addr[3]~13COUT1_64 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[4]),
	.cout(\Addr[4]~17 ),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Addr[4] .cin0_used = "true";
defparam \Addr[4] .cin1_used = "true";
defparam \Addr[4] .lut_mask = "a50a";
defparam \Addr[4] .operation_mode = "arithmetic";
defparam \Addr[4] .output_mode = "reg_only";
defparam \Addr[4] .register_cascade_mode = "off";
defparam \Addr[4] .sum_lutc_input = "cin";
defparam \Addr[4] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X6_Y3_N5
maxii_lcell \Addr[5] (
// Equation(s):
// Addr[5] = DFFEAS(Addr[5] $ ((((\Addr[4]~17 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[5]~5 , , , \always9~4_combout )
// \Addr[5]~21  = CARRY(((!\Addr[4]~17 )) # (!Addr[5]))
// \Addr[5]~21COUT1_65  = CARRY(((!\Addr[4]~17 )) # (!Addr[5]))

	.clk(\C25M~combout ),
	.dataa(Addr[5]),
	.datab(vcc),
	.datac(\RD[5]~5 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~4_combout ),
	.ena(vcc),
	.cin(\Addr[4]~17 ),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[5]),
	.cout(),
	.cout0(\Addr[5]~21 ),
	.cout1(\Addr[5]~21COUT1_65 ));
// synopsys translate_off
defparam \Addr[5] .cin_used = "true";
defparam \Addr[5] .lut_mask = "5a5f";
defparam \Addr[5] .operation_mode = "arithmetic";
defparam \Addr[5] .output_mode = "reg_only";
defparam \Addr[5] .register_cascade_mode = "off";
defparam \Addr[5] .sum_lutc_input = "cin";
defparam \Addr[5] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X6_Y3_N6
maxii_lcell \Addr[6] (
// Equation(s):
// Addr[6] = DFFEAS((Addr[6] $ ((!(!\Addr[4]~17  & \Addr[5]~21 ) # (\Addr[4]~17  & \Addr[5]~21COUT1_65 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[6]~6 , , , \always9~4_combout )
// \Addr[6]~25  = CARRY(((Addr[6] & !\Addr[5]~21 )))
// \Addr[6]~25COUT1_66  = CARRY(((Addr[6] & !\Addr[5]~21COUT1_65 )))

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(Addr[6]),
	.datac(\RD[6]~6 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~4_combout ),
	.ena(vcc),
	.cin(\Addr[4]~17 ),
	.cin0(\Addr[5]~21 ),
	.cin1(\Addr[5]~21COUT1_65 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[6]),
	.cout(),
	.cout0(\Addr[6]~25 ),
	.cout1(\Addr[6]~25COUT1_66 ));
// synopsys translate_off
defparam \Addr[6] .cin0_used = "true";
defparam \Addr[6] .cin1_used = "true";
defparam \Addr[6] .cin_used = "true";
defparam \Addr[6] .lut_mask = "c30c";
defparam \Addr[6] .operation_mode = "arithmetic";
defparam \Addr[6] .output_mode = "reg_only";
defparam \Addr[6] .register_cascade_mode = "off";
defparam \Addr[6] .sum_lutc_input = "cin";
defparam \Addr[6] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X6_Y3_N7
maxii_lcell \Addr[7] (
// Equation(s):
// Addr[7] = DFFEAS((Addr[7] $ (((!\Addr[4]~17  & \Addr[6]~25 ) # (\Addr[4]~17  & \Addr[6]~25COUT1_66 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[7]~7 , , , \always9~4_combout )

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(Addr[7]),
	.datac(\RD[7]~7 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~4_combout ),
	.ena(vcc),
	.cin(\Addr[4]~17 ),
	.cin0(\Addr[6]~25 ),
	.cin1(\Addr[6]~25COUT1_66 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[7]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Addr[7] .cin0_used = "true";
defparam \Addr[7] .cin1_used = "true";
defparam \Addr[7] .cin_used = "true";
defparam \Addr[7] .lut_mask = "3c3c";
defparam \Addr[7] .operation_mode = "normal";
defparam \Addr[7] .output_mode = "reg_only";
defparam \Addr[7] .register_cascade_mode = "off";
defparam \Addr[7] .sum_lutc_input = "cin";
defparam \Addr[7] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X6_Y3_N8
maxii_lcell \AddrIncM~1 (
// Equation(s):
// \AddrIncM~1_combout  = (Addr[5] & (Addr[6] & (Addr[4] & Addr[3])))

	.clk(gnd),
	.dataa(Addr[5]),
	.datab(Addr[6]),
	.datac(Addr[4]),
	.datad(Addr[3]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\AddrIncM~1_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \AddrIncM~1 .lut_mask = "8000";
defparam \AddrIncM~1 .operation_mode = "normal";
defparam \AddrIncM~1 .output_mode = "comb_only";
defparam \AddrIncM~1 .register_cascade_mode = "off";
defparam \AddrIncM~1 .sum_lutc_input = "datac";
defparam \AddrIncM~1 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y3_N3
maxii_lcell \AddrIncM~0 (
// Equation(s):
// \AddrIncM~0_combout  = ((\AddrIncL~regout  & (Addr[0])))

	.clk(gnd),
	.dataa(vcc),
	.datab(\AddrIncL~regout ),
	.datac(Addr[0]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\AddrIncM~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \AddrIncM~0 .lut_mask = "c0c0";
defparam \AddrIncM~0 .operation_mode = "normal";
defparam \AddrIncM~0 .output_mode = "comb_only";
defparam \AddrIncM~0 .register_cascade_mode = "off";
defparam \AddrIncM~0 .sum_lutc_input = "datac";
defparam \AddrIncM~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y3_N6
maxii_lcell \AddrIncM~2 (
// Equation(s):
// \AddrIncM~2_combout  = (Addr[1] & (Addr[2] & (\AddrIncM~1_combout  & \AddrIncM~0_combout )))

	.clk(gnd),
	.dataa(Addr[1]),
	.datab(Addr[2]),
	.datac(\AddrIncM~1_combout ),
	.datad(\AddrIncM~0_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\AddrIncM~2_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \AddrIncM~2 .lut_mask = "8000";
defparam \AddrIncM~2 .operation_mode = "normal";
defparam \AddrIncM~2 .output_mode = "comb_only";
defparam \AddrIncM~2 .register_cascade_mode = "off";
defparam \AddrIncM~2 .sum_lutc_input = "datac";
defparam \AddrIncM~2 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y2_N9
maxii_lcell AddrIncM(
// Equation(s):
// \AddrIncM~regout  = DFFEAS((Addr[7] & ((\always9~4_combout  & ((!\RD[7]~7 ))) # (!\always9~4_combout  & (\AddrIncM~2_combout )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , , , , )

	.clk(\C25M~combout ),
	.dataa(Addr[7]),
	.datab(\AddrIncM~2_combout ),
	.datac(\RD[7]~7 ),
	.datad(\always9~4_combout ),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\AddrIncM~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam AddrIncM.lut_mask = "0a88";
defparam AddrIncM.operation_mode = "normal";
defparam AddrIncM.output_mode = "reg_only";
defparam AddrIncM.register_cascade_mode = "off";
defparam AddrIncM.sum_lutc_input = "datac";
defparam AddrIncM.synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y2_N0
maxii_lcell \Addr[8] (
// Equation(s):
// Addr[8] = DFFEAS(\AddrIncM~regout  $ ((Addr[8])), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[0]~0 , , , \always9~3_combout )
// \Addr[8]~33  = CARRY((\AddrIncM~regout  & (Addr[8])))
// \Addr[8]~33COUT1_55  = CARRY((\AddrIncM~regout  & (Addr[8])))

	.clk(\C25M~combout ),
	.dataa(\AddrIncM~regout ),
	.datab(Addr[8]),
	.datac(\RD[0]~0 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~3_combout ),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[8]),
	.cout(),
	.cout0(\Addr[8]~33 ),
	.cout1(\Addr[8]~33COUT1_55 ));
// synopsys translate_off
defparam \Addr[8] .lut_mask = "6688";
defparam \Addr[8] .operation_mode = "arithmetic";
defparam \Addr[8] .output_mode = "reg_only";
defparam \Addr[8] .register_cascade_mode = "off";
defparam \Addr[8] .sum_lutc_input = "datac";
defparam \Addr[8] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X5_Y2_N1
maxii_lcell \Addr[9] (
// Equation(s):
// Addr[9] = DFFEAS((Addr[9] $ ((\Addr[8]~33 ))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[1]~1 , , , \always9~3_combout )
// \Addr[9]~37  = CARRY(((!\Addr[8]~33 ) # (!Addr[9])))
// \Addr[9]~37COUT1_56  = CARRY(((!\Addr[8]~33COUT1_55 ) # (!Addr[9])))

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(Addr[9]),
	.datac(\RD[1]~1 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~3_combout ),
	.ena(vcc),
	.cin(gnd),
	.cin0(\Addr[8]~33 ),
	.cin1(\Addr[8]~33COUT1_55 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[9]),
	.cout(),
	.cout0(\Addr[9]~37 ),
	.cout1(\Addr[9]~37COUT1_56 ));
// synopsys translate_off
defparam \Addr[9] .cin0_used = "true";
defparam \Addr[9] .cin1_used = "true";
defparam \Addr[9] .lut_mask = "3c3f";
defparam \Addr[9] .operation_mode = "arithmetic";
defparam \Addr[9] .output_mode = "reg_only";
defparam \Addr[9] .register_cascade_mode = "off";
defparam \Addr[9] .sum_lutc_input = "cin";
defparam \Addr[9] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X5_Y2_N2
maxii_lcell \Addr[10] (
// Equation(s):
// Addr[10] = DFFEAS((Addr[10] $ ((!\Addr[9]~37 ))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[2]~2 , , , \always9~3_combout )
// \Addr[10]~3  = CARRY(((Addr[10] & !\Addr[9]~37 )))
// \Addr[10]~3COUT1_57  = CARRY(((Addr[10] & !\Addr[9]~37COUT1_56 )))

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(Addr[10]),
	.datac(\RD[2]~2 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~3_combout ),
	.ena(vcc),
	.cin(gnd),
	.cin0(\Addr[9]~37 ),
	.cin1(\Addr[9]~37COUT1_56 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[10]),
	.cout(),
	.cout0(\Addr[10]~3 ),
	.cout1(\Addr[10]~3COUT1_57 ));
// synopsys translate_off
defparam \Addr[10] .cin0_used = "true";
defparam \Addr[10] .cin1_used = "true";
defparam \Addr[10] .lut_mask = "c30c";
defparam \Addr[10] .operation_mode = "arithmetic";
defparam \Addr[10] .output_mode = "reg_only";
defparam \Addr[10] .register_cascade_mode = "off";
defparam \Addr[10] .sum_lutc_input = "cin";
defparam \Addr[10] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X3_Y2_N4
maxii_lcell \RAr[10] (
// Equation(s):
// \Mux24~2  = (\SA[1]~2_combout  & (\Mux24~1_combout )) # (!\SA[1]~2_combout  & ((\Mux24~1_combout  & (RAr[10])) # (!\Mux24~1_combout  & ((Addr[10])))))
// RAr[10] = DFFEAS(\Mux24~2 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [10], , , VCC)

	.clk(\PHI0~combout ),
	.dataa(\SA[1]~2_combout ),
	.datab(\Mux24~1_combout ),
	.datac(\RA~combout [10]),
	.datad(Addr[10]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux24~2 ),
	.regout(RAr[10]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RAr[10] .lut_mask = "d9c8";
defparam \RAr[10] .operation_mode = "normal";
defparam \RAr[10] .output_mode = "reg_and_comb";
defparam \RAr[10] .register_cascade_mode = "off";
defparam \RAr[10] .sum_lutc_input = "qfbk";
defparam \RAr[10] .synch_mode = "on";
// synopsys translate_on

// Location: PIN_8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \RA[9]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\RA~combout [9]),
	.padio(RA[9]));
// synopsys translate_off
defparam \RA[9]~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X3_Y2_N2
maxii_lcell \RAr[9] (
// Equation(s):
// \Mux16~2  = (((RAr[9] & !PS[0])))
// RAr[9] = DFFEAS(\Mux16~2 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [9], , , VCC)

	.clk(\PHI0~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\RA~combout [9]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux16~2 ),
	.regout(RAr[9]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RAr[9] .lut_mask = "00f0";
defparam \RAr[9] .operation_mode = "normal";
defparam \RAr[9] .output_mode = "reg_and_comb";
defparam \RAr[9] .register_cascade_mode = "off";
defparam \RAr[9] .sum_lutc_input = "qfbk";
defparam \RAr[9] .synch_mode = "on";
// synopsys translate_on

// Location: PIN_6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \RA[7]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\RA~combout [7]),
	.padio(RA[7]));
// synopsys translate_off
defparam \RA[7]~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X5_Y2_N3
maxii_lcell \Addr[11] (
// Equation(s):
// Addr[11] = DFFEAS(Addr[11] $ ((((\Addr[10]~3 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[3]~3 , , , \always9~3_combout )
// \Addr[11]~7  = CARRY(((!\Addr[10]~3 )) # (!Addr[11]))
// \Addr[11]~7COUT1_58  = CARRY(((!\Addr[10]~3COUT1_57 )) # (!Addr[11]))

	.clk(\C25M~combout ),
	.dataa(Addr[11]),
	.datab(vcc),
	.datac(\RD[3]~3 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~3_combout ),
	.ena(vcc),
	.cin(gnd),
	.cin0(\Addr[10]~3 ),
	.cin1(\Addr[10]~3COUT1_57 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[11]),
	.cout(),
	.cout0(\Addr[11]~7 ),
	.cout1(\Addr[11]~7COUT1_58 ));
// synopsys translate_off
defparam \Addr[11] .cin0_used = "true";
defparam \Addr[11] .cin1_used = "true";
defparam \Addr[11] .lut_mask = "5a5f";
defparam \Addr[11] .operation_mode = "arithmetic";
defparam \Addr[11] .output_mode = "reg_only";
defparam \Addr[11] .register_cascade_mode = "off";
defparam \Addr[11] .sum_lutc_input = "cin";
defparam \Addr[11] .synch_mode = "on";
// synopsys translate_on

// Location: PIN_34,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \RA[11]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\RA~combout [11]),
	.padio(RA[11]));
// synopsys translate_off
defparam \RA[11]~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X3_Y2_N8
maxii_lcell \Mux23~0 (
// Equation(s):
// \Mux23~0_combout  = ((LS[11] & ((PS[0]))))

	.clk(gnd),
	.dataa(vcc),
	.datab(LS[11]),
	.datac(vcc),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux23~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux23~0 .lut_mask = "cc00";
defparam \Mux23~0 .operation_mode = "normal";
defparam \Mux23~0 .output_mode = "comb_only";
defparam \Mux23~0 .register_cascade_mode = "off";
defparam \Mux23~0 .sum_lutc_input = "datac";
defparam \Mux23~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y2_N1
maxii_lcell \Mux23~1 (
// Equation(s):
// \Mux23~1_combout  = (\SA[1]~3_combout  & ((\SA[1]~4_combout  & ((RAr[2]))) # (!\SA[1]~4_combout  & (\Mux23~0_combout )))) # (!\SA[1]~3_combout  & (!\SA[1]~4_combout ))

	.clk(gnd),
	.dataa(\SA[1]~3_combout ),
	.datab(\SA[1]~4_combout ),
	.datac(\Mux23~0_combout ),
	.datad(RAr[2]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux23~1_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux23~1 .lut_mask = "b931";
defparam \Mux23~1 .operation_mode = "normal";
defparam \Mux23~1 .output_mode = "comb_only";
defparam \Mux23~1 .register_cascade_mode = "off";
defparam \Mux23~1 .sum_lutc_input = "datac";
defparam \Mux23~1 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y2_N7
maxii_lcell \RAr[11] (
// Equation(s):
// \Mux23~2  = (\SA[1]~2_combout  & (((\Mux23~1_combout )))) # (!\SA[1]~2_combout  & ((\Mux23~1_combout  & ((RAr[11]))) # (!\Mux23~1_combout  & (Addr[11]))))
// RAr[11] = DFFEAS(\Mux23~2 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [11], , , VCC)

	.clk(\PHI0~combout ),
	.dataa(\SA[1]~2_combout ),
	.datab(Addr[11]),
	.datac(\RA~combout [11]),
	.datad(\Mux23~1_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux23~2 ),
	.regout(RAr[11]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RAr[11] .lut_mask = "fa44";
defparam \RAr[11] .operation_mode = "normal";
defparam \RAr[11] .output_mode = "reg_and_comb";
defparam \RAr[11] .register_cascade_mode = "off";
defparam \RAr[11] .sum_lutc_input = "qfbk";
defparam \RAr[11] .synch_mode = "on";
// synopsys translate_on

// Location: PIN_7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \RA[8]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\RA~combout [8]),
	.padio(RA[8]));
// synopsys translate_off
defparam \RA[8]~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X3_Y2_N6
maxii_lcell \RAr[8] (
// Equation(s):
// \Equal9~0  = (!RAr[10] & (!RAr[11] & (!RAr[8] & !RAr[9])))
// RAr[8] = DFFEAS(\Equal9~0 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [8], , , VCC)

	.clk(\PHI0~combout ),
	.dataa(RAr[10]),
	.datab(RAr[11]),
	.datac(\RA~combout [8]),
	.datad(RAr[9]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Equal9~0 ),
	.regout(RAr[8]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RAr[8] .lut_mask = "0001";
defparam \RAr[8] .operation_mode = "normal";
defparam \RAr[8] .output_mode = "reg_and_comb";
defparam \RAr[8] .register_cascade_mode = "off";
defparam \RAr[8] .sum_lutc_input = "qfbk";
defparam \RAr[8] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X3_Y2_N0
maxii_lcell \RAr[7] (
// Equation(s):
// \always8~2  = (RAr[10] & (RAr[9] & (RAr[7] & RAr[8])))
// RAr[7] = DFFEAS(\always8~2 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [7], , , VCC)

	.clk(\PHI0~combout ),
	.dataa(RAr[10]),
	.datab(RAr[9]),
	.datac(\RA~combout [7]),
	.datad(RAr[8]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\always8~2 ),
	.regout(RAr[7]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RAr[7] .lut_mask = "8000";
defparam \RAr[7] .operation_mode = "normal";
defparam \RAr[7] .output_mode = "reg_and_comb";
defparam \RAr[7] .register_cascade_mode = "off";
defparam \RAr[7] .sum_lutc_input = "qfbk";
defparam \RAr[7] .synch_mode = "on";
// synopsys translate_on

// Location: PIN_39,	 I/O Standard: 3.3V Schmitt Trigger Input,	 Current Strength: Default
maxii_io \nIOSEL~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\nIOSEL~combout ),
	.padio(nIOSEL));
// synopsys translate_off
defparam \nIOSEL~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X4_Y1_N0
maxii_lcell REGEN(
// Equation(s):
// \REGEN~regout  = DFFEAS(((\REGEN~regout ) # ((\Equal19~0_combout  & !\nIOSEL~combout ))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , , , , )

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(\REGEN~regout ),
	.datac(\Equal19~0_combout ),
	.datad(\nIOSEL~combout ),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\REGEN~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam REGEN.lut_mask = "ccfc";
defparam REGEN.operation_mode = "normal";
defparam REGEN.output_mode = "reg_only";
defparam REGEN.register_cascade_mode = "off";
defparam REGEN.sum_lutc_input = "datac";
defparam REGEN.synch_mode = "off";
// synopsys translate_on

// Location: PIN_37,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \RA[14]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\RA~combout [14]),
	.padio(RA[14]));
// synopsys translate_off
defparam \RA[14]~I .operation_mode = "input";
// synopsys translate_on

// Location: PIN_35,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \RA[12]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\RA~combout [12]),
	.padio(RA[12]));
// synopsys translate_off
defparam \RA[12]~I .operation_mode = "input";
// synopsys translate_on

// Location: PIN_38,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \RA[15]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\RA~combout [15]),
	.padio(RA[15]));
// synopsys translate_off
defparam \RA[15]~I .operation_mode = "input";
// synopsys translate_on

// Location: PIN_36,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \RA[13]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\RA~combout [13]),
	.padio(RA[13]));
// synopsys translate_off
defparam \RA[13]~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X4_Y1_N6
maxii_lcell CXXXr(
// Equation(s):
// \CXXXr~regout  = DFFEAS((\RA~combout [14] & (!\RA~combout [12] & (\RA~combout [15] & !\RA~combout [13]))), GLOBAL(\PHI0~combout ), VCC, , , , , , )

	.clk(\PHI0~combout ),
	.dataa(\RA~combout [14]),
	.datab(\RA~combout [12]),
	.datac(\RA~combout [15]),
	.datad(\RA~combout [13]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\CXXXr~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam CXXXr.lut_mask = "0020";
defparam CXXXr.operation_mode = "normal";
defparam CXXXr.output_mode = "reg_only";
defparam CXXXr.register_cascade_mode = "off";
defparam CXXXr.sum_lutc_input = "datac";
defparam CXXXr.synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y1_N5
maxii_lcell \always9~0 (
// Equation(s):
// \always9~0_combout  = (RAr[7] & (\REGEN~regout  & (\CXXXr~regout  & \Equal9~0 )))

	.clk(gnd),
	.dataa(RAr[7]),
	.datab(\REGEN~regout ),
	.datac(\CXXXr~regout ),
	.datad(\Equal9~0 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\always9~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \always9~0 .lut_mask = "8000";
defparam \always9~0 .operation_mode = "normal";
defparam \always9~0 .output_mode = "comb_only";
defparam \always9~0 .register_cascade_mode = "off";
defparam \always9~0 .sum_lutc_input = "datac";
defparam \always9~0 .synch_mode = "off";
// synopsys translate_on

// Location: PIN_96,	 I/O Standard: 3.3V Schmitt Trigger Input,	 Current Strength: Default
maxii_io \SetFW[0]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\SetFW~combout [0]),
	.padio(SetFW[0]));
// synopsys translate_off
defparam \SetFW[0]~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X4_Y2_N8
maxii_lcell SetFWLoaded(
// Equation(s):
// \SetFWLoaded~regout  = DFFEAS(VCC, GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SetFWLoaded~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam SetFWLoaded.lut_mask = "ffff";
defparam SetFWLoaded.operation_mode = "normal";
defparam SetFWLoaded.output_mode = "reg_only";
defparam SetFWLoaded.register_cascade_mode = "off";
defparam SetFWLoaded.sum_lutc_input = "datac";
defparam SetFWLoaded.synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y2_N7
maxii_lcell \SetFWr[0] (
// Equation(s):
// \Mux2~2  = (LS[1] & (((!LS[2])))) # (!LS[1] & (\Equal1~0_combout  & (!SetFWr[0] & LS[2])))
// SetFWr[0] = DFFEAS(\Mux2~2 , GLOBAL(\C25M~combout ), VCC, , !\SetFWLoaded~regout , \SetFW~combout [0], , , VCC)

	.clk(\C25M~combout ),
	.dataa(LS[1]),
	.datab(\Equal1~0_combout ),
	.datac(\SetFW~combout [0]),
	.datad(LS[2]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(!\SetFWLoaded~regout ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux2~2 ),
	.regout(SetFWr[0]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SetFWr[0] .lut_mask = "04aa";
defparam \SetFWr[0] .operation_mode = "normal";
defparam \SetFWr[0] .output_mode = "reg_and_comb";
defparam \SetFWr[0] .register_cascade_mode = "off";
defparam \SetFWr[0] .sum_lutc_input = "qfbk";
defparam \SetFWr[0] .synch_mode = "on";
// synopsys translate_on

// Location: PIN_95,	 I/O Standard: 3.3V Schmitt Trigger Input,	 Current Strength: Default
maxii_io \SetFW[1]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\SetFW~combout [1]),
	.padio(SetFW[1]));
// synopsys translate_off
defparam \SetFW[1]~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X7_Y3_N6
maxii_lcell \always9~2 (
// Equation(s):
// \always9~2_combout  = (\always9~1_combout  & (!RAr[0] & (RAr[1] & \RAMRegSpecSEL~1 )))

	.clk(gnd),
	.dataa(\always9~1_combout ),
	.datab(RAr[0]),
	.datac(RAr[1]),
	.datad(\RAMRegSpecSEL~1 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\always9~2_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \always9~2 .lut_mask = "2000";
defparam \always9~2 .operation_mode = "normal";
defparam \always9~2 .output_mode = "comb_only";
defparam \always9~2 .register_cascade_mode = "off";
defparam \always9~2 .sum_lutc_input = "datac";
defparam \always9~2 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y2_N9
maxii_lcell \AddrIncH~0 (
// Equation(s):
// \AddrIncH~0_combout  = ((\AddrIncM~regout  & (Addr[8])))

	.clk(gnd),
	.dataa(vcc),
	.datab(\AddrIncM~regout ),
	.datac(Addr[8]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\AddrIncH~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \AddrIncH~0 .lut_mask = "c0c0";
defparam \AddrIncH~0 .operation_mode = "normal";
defparam \AddrIncH~0 .output_mode = "comb_only";
defparam \AddrIncH~0 .register_cascade_mode = "off";
defparam \AddrIncH~0 .sum_lutc_input = "datac";
defparam \AddrIncH~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y2_N4
maxii_lcell \Addr[12] (
// Equation(s):
// Addr[12] = DFFEAS(Addr[12] $ ((((!\Addr[11]~7 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[4]~4 , , , \always9~3_combout )
// \Addr[12]~11  = CARRY((Addr[12] & ((!\Addr[11]~7COUT1_58 ))))

	.clk(\C25M~combout ),
	.dataa(Addr[12]),
	.datab(vcc),
	.datac(\RD[4]~4 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~3_combout ),
	.ena(vcc),
	.cin(gnd),
	.cin0(\Addr[11]~7 ),
	.cin1(\Addr[11]~7COUT1_58 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[12]),
	.cout(\Addr[12]~11 ),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Addr[12] .cin0_used = "true";
defparam \Addr[12] .cin1_used = "true";
defparam \Addr[12] .lut_mask = "a50a";
defparam \Addr[12] .operation_mode = "arithmetic";
defparam \Addr[12] .output_mode = "reg_only";
defparam \Addr[12] .register_cascade_mode = "off";
defparam \Addr[12] .sum_lutc_input = "cin";
defparam \Addr[12] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X5_Y2_N5
maxii_lcell \Addr[13] (
// Equation(s):
// Addr[13] = DFFEAS(Addr[13] $ ((((\Addr[12]~11 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[5]~5 , , , \always9~3_combout )
// \Addr[13]~15  = CARRY(((!\Addr[12]~11 )) # (!Addr[13]))
// \Addr[13]~15COUT1_59  = CARRY(((!\Addr[12]~11 )) # (!Addr[13]))

	.clk(\C25M~combout ),
	.dataa(Addr[13]),
	.datab(vcc),
	.datac(\RD[5]~5 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~3_combout ),
	.ena(vcc),
	.cin(\Addr[12]~11 ),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[13]),
	.cout(),
	.cout0(\Addr[13]~15 ),
	.cout1(\Addr[13]~15COUT1_59 ));
// synopsys translate_off
defparam \Addr[13] .cin_used = "true";
defparam \Addr[13] .lut_mask = "5a5f";
defparam \Addr[13] .operation_mode = "arithmetic";
defparam \Addr[13] .output_mode = "reg_only";
defparam \Addr[13] .register_cascade_mode = "off";
defparam \Addr[13] .sum_lutc_input = "cin";
defparam \Addr[13] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X5_Y2_N6
maxii_lcell \Addr[14] (
// Equation(s):
// Addr[14] = DFFEAS(Addr[14] $ ((((!(!\Addr[12]~11  & \Addr[13]~15 ) # (\Addr[12]~11  & \Addr[13]~15COUT1_59 ))))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[6]~6 , , , \always9~3_combout )
// \Addr[14]~19  = CARRY((Addr[14] & ((!\Addr[13]~15 ))))
// \Addr[14]~19COUT1_60  = CARRY((Addr[14] & ((!\Addr[13]~15COUT1_59 ))))

	.clk(\C25M~combout ),
	.dataa(Addr[14]),
	.datab(vcc),
	.datac(\RD[6]~6 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~3_combout ),
	.ena(vcc),
	.cin(\Addr[12]~11 ),
	.cin0(\Addr[13]~15 ),
	.cin1(\Addr[13]~15COUT1_59 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[14]),
	.cout(),
	.cout0(\Addr[14]~19 ),
	.cout1(\Addr[14]~19COUT1_60 ));
// synopsys translate_off
defparam \Addr[14] .cin0_used = "true";
defparam \Addr[14] .cin1_used = "true";
defparam \Addr[14] .cin_used = "true";
defparam \Addr[14] .lut_mask = "a50a";
defparam \Addr[14] .operation_mode = "arithmetic";
defparam \Addr[14] .output_mode = "reg_only";
defparam \Addr[14] .register_cascade_mode = "off";
defparam \Addr[14] .sum_lutc_input = "cin";
defparam \Addr[14] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X5_Y2_N8
maxii_lcell \AddrIncH~1 (
// Equation(s):
// \AddrIncH~1_combout  = (Addr[13] & (Addr[12] & (Addr[14] & Addr[11])))

	.clk(gnd),
	.dataa(Addr[13]),
	.datab(Addr[12]),
	.datac(Addr[14]),
	.datad(Addr[11]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\AddrIncH~1_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \AddrIncH~1 .lut_mask = "8000";
defparam \AddrIncH~1 .operation_mode = "normal";
defparam \AddrIncH~1 .output_mode = "comb_only";
defparam \AddrIncH~1 .register_cascade_mode = "off";
defparam \AddrIncH~1 .sum_lutc_input = "datac";
defparam \AddrIncH~1 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y2_N4
maxii_lcell \AddrIncH~2 (
// Equation(s):
// \AddrIncH~2_combout  = (Addr[9] & (\AddrIncH~0_combout  & (Addr[10] & \AddrIncH~1_combout )))

	.clk(gnd),
	.dataa(Addr[9]),
	.datab(\AddrIncH~0_combout ),
	.datac(Addr[10]),
	.datad(\AddrIncH~1_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\AddrIncH~2_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \AddrIncH~2 .lut_mask = "8000";
defparam \AddrIncH~2 .operation_mode = "normal";
defparam \AddrIncH~2 .output_mode = "comb_only";
defparam \AddrIncH~2 .register_cascade_mode = "off";
defparam \AddrIncH~2 .sum_lutc_input = "datac";
defparam \AddrIncH~2 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y2_N7
maxii_lcell \Addr[15] (
// Equation(s):
// Addr[15] = DFFEAS((Addr[15] $ (((!\Addr[12]~11  & \Addr[14]~19 ) # (\Addr[12]~11  & \Addr[14]~19COUT1_60 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[7]~7 , , , \always9~3_combout )

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(Addr[15]),
	.datac(\RD[7]~7 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~3_combout ),
	.ena(vcc),
	.cin(\Addr[12]~11 ),
	.cin0(\Addr[14]~19 ),
	.cin1(\Addr[14]~19COUT1_60 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[15]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Addr[15] .cin0_used = "true";
defparam \Addr[15] .cin1_used = "true";
defparam \Addr[15] .cin_used = "true";
defparam \Addr[15] .lut_mask = "3c3c";
defparam \Addr[15] .operation_mode = "normal";
defparam \Addr[15] .output_mode = "reg_only";
defparam \Addr[15] .register_cascade_mode = "off";
defparam \Addr[15] .sum_lutc_input = "cin";
defparam \Addr[15] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X6_Y2_N2
maxii_lcell AddrIncH(
// Equation(s):
// \AddrIncH~regout  = DFFEAS((Addr[15] & ((\always9~3_combout  & ((!\RD[7]~7 ))) # (!\always9~3_combout  & (\AddrIncH~2_combout )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , , , , )

	.clk(\C25M~combout ),
	.dataa(\AddrIncH~2_combout ),
	.datab(\always9~3_combout ),
	.datac(\RD[7]~7 ),
	.datad(Addr[15]),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\AddrIncH~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam AddrIncH.lut_mask = "2e00";
defparam AddrIncH.operation_mode = "normal";
defparam AddrIncH.output_mode = "reg_only";
defparam AddrIncH.register_cascade_mode = "off";
defparam AddrIncH.sum_lutc_input = "datac";
defparam AddrIncH.synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y4_N0
maxii_lcell \Addr[16] (
// Equation(s):
// Addr[16] = DFFEAS(\AddrIncH~regout  $ ((Addr[16])), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[0]~0 , , , \always9~2_combout )
// \Addr[16]~27  = CARRY((\AddrIncH~regout  & (Addr[16])))
// \Addr[16]~27COUT1_49  = CARRY((\AddrIncH~regout  & (Addr[16])))

	.clk(\C25M~combout ),
	.dataa(\AddrIncH~regout ),
	.datab(Addr[16]),
	.datac(\RD[0]~0 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~2_combout ),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[16]),
	.cout(),
	.cout0(\Addr[16]~27 ),
	.cout1(\Addr[16]~27COUT1_49 ));
// synopsys translate_off
defparam \Addr[16] .lut_mask = "6688";
defparam \Addr[16] .operation_mode = "arithmetic";
defparam \Addr[16] .output_mode = "reg_only";
defparam \Addr[16] .register_cascade_mode = "off";
defparam \Addr[16] .sum_lutc_input = "datac";
defparam \Addr[16] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X7_Y4_N1
maxii_lcell \Addr[17] (
// Equation(s):
// Addr[17] = DFFEAS((Addr[17] $ ((\Addr[16]~27 ))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[1]~1 , , , \always9~2_combout )
// \Addr[17]~31  = CARRY(((!\Addr[16]~27 ) # (!Addr[17])))
// \Addr[17]~31COUT1_50  = CARRY(((!\Addr[16]~27COUT1_49 ) # (!Addr[17])))

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(Addr[17]),
	.datac(\RD[1]~1 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~2_combout ),
	.ena(vcc),
	.cin(gnd),
	.cin0(\Addr[16]~27 ),
	.cin1(\Addr[16]~27COUT1_49 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[17]),
	.cout(),
	.cout0(\Addr[17]~31 ),
	.cout1(\Addr[17]~31COUT1_50 ));
// synopsys translate_off
defparam \Addr[17] .cin0_used = "true";
defparam \Addr[17] .cin1_used = "true";
defparam \Addr[17] .lut_mask = "3c3f";
defparam \Addr[17] .operation_mode = "arithmetic";
defparam \Addr[17] .output_mode = "reg_only";
defparam \Addr[17] .register_cascade_mode = "off";
defparam \Addr[17] .sum_lutc_input = "cin";
defparam \Addr[17] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X7_Y4_N2
maxii_lcell \Addr[18] (
// Equation(s):
// Addr[18] = DFFEAS((Addr[18] $ ((!\Addr[17]~31 ))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[2]~2 , , , \always9~2_combout )
// \Addr[18]~35  = CARRY(((Addr[18] & !\Addr[17]~31 )))
// \Addr[18]~35COUT1_51  = CARRY(((Addr[18] & !\Addr[17]~31COUT1_50 )))

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(Addr[18]),
	.datac(\RD[2]~2 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~2_combout ),
	.ena(vcc),
	.cin(gnd),
	.cin0(\Addr[17]~31 ),
	.cin1(\Addr[17]~31COUT1_50 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[18]),
	.cout(),
	.cout0(\Addr[18]~35 ),
	.cout1(\Addr[18]~35COUT1_51 ));
// synopsys translate_off
defparam \Addr[18] .cin0_used = "true";
defparam \Addr[18] .cin1_used = "true";
defparam \Addr[18] .lut_mask = "c30c";
defparam \Addr[18] .operation_mode = "arithmetic";
defparam \Addr[18] .output_mode = "reg_only";
defparam \Addr[18] .register_cascade_mode = "off";
defparam \Addr[18] .sum_lutc_input = "cin";
defparam \Addr[18] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X7_Y4_N3
maxii_lcell \Addr[19] (
// Equation(s):
// Addr[19] = DFFEAS(Addr[19] $ ((((\Addr[18]~35 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[3]~3 , , , \always9~2_combout )
// \Addr[19]~39  = CARRY(((!\Addr[18]~35 )) # (!Addr[19]))
// \Addr[19]~39COUT1_52  = CARRY(((!\Addr[18]~35COUT1_51 )) # (!Addr[19]))

	.clk(\C25M~combout ),
	.dataa(Addr[19]),
	.datab(vcc),
	.datac(\RD[3]~3 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~2_combout ),
	.ena(vcc),
	.cin(gnd),
	.cin0(\Addr[18]~35 ),
	.cin1(\Addr[18]~35COUT1_51 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[19]),
	.cout(),
	.cout0(\Addr[19]~39 ),
	.cout1(\Addr[19]~39COUT1_52 ));
// synopsys translate_off
defparam \Addr[19] .cin0_used = "true";
defparam \Addr[19] .cin1_used = "true";
defparam \Addr[19] .lut_mask = "5a5f";
defparam \Addr[19] .operation_mode = "arithmetic";
defparam \Addr[19] .output_mode = "reg_only";
defparam \Addr[19] .register_cascade_mode = "off";
defparam \Addr[19] .sum_lutc_input = "cin";
defparam \Addr[19] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X7_Y4_N4
maxii_lcell \Addr[20] (
// Equation(s):
// Addr[20] = DFFEAS(Addr[20] $ ((((!\Addr[19]~39 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[4]~4 , , , \always9~2_combout )
// \Addr[20]~41  = CARRY((Addr[20] & ((!\Addr[19]~39COUT1_52 ))))

	.clk(\C25M~combout ),
	.dataa(Addr[20]),
	.datab(vcc),
	.datac(\RD[4]~4 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~2_combout ),
	.ena(vcc),
	.cin(gnd),
	.cin0(\Addr[19]~39 ),
	.cin1(\Addr[19]~39COUT1_52 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[20]),
	.cout(\Addr[20]~41 ),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Addr[20] .cin0_used = "true";
defparam \Addr[20] .cin1_used = "true";
defparam \Addr[20] .lut_mask = "a50a";
defparam \Addr[20] .operation_mode = "arithmetic";
defparam \Addr[20] .output_mode = "reg_only";
defparam \Addr[20] .register_cascade_mode = "off";
defparam \Addr[20] .sum_lutc_input = "cin";
defparam \Addr[20] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X7_Y4_N5
maxii_lcell \Addr[21] (
// Equation(s):
// Addr[21] = DFFEAS(Addr[21] $ ((((\Addr[20]~41 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[5]~5 , , , \always9~2_combout )
// \Addr[21]~43  = CARRY(((!\Addr[20]~41 )) # (!Addr[21]))
// \Addr[21]~43COUT1_53  = CARRY(((!\Addr[20]~41 )) # (!Addr[21]))

	.clk(\C25M~combout ),
	.dataa(Addr[21]),
	.datab(vcc),
	.datac(\RD[5]~5 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~2_combout ),
	.ena(vcc),
	.cin(\Addr[20]~41 ),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[21]),
	.cout(),
	.cout0(\Addr[21]~43 ),
	.cout1(\Addr[21]~43COUT1_53 ));
// synopsys translate_off
defparam \Addr[21] .cin_used = "true";
defparam \Addr[21] .lut_mask = "5a5f";
defparam \Addr[21] .operation_mode = "arithmetic";
defparam \Addr[21] .output_mode = "reg_only";
defparam \Addr[21] .register_cascade_mode = "off";
defparam \Addr[21] .sum_lutc_input = "cin";
defparam \Addr[21] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X7_Y4_N6
maxii_lcell \Addr[22] (
// Equation(s):
// Addr[22] = DFFEAS(Addr[22] $ ((((!(!\Addr[20]~41  & \Addr[21]~43 ) # (\Addr[20]~41  & \Addr[21]~43COUT1_53 ))))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[6]~6 , , , \always9~2_combout )
// \Addr[22]~45  = CARRY((Addr[22] & ((!\Addr[21]~43 ))))
// \Addr[22]~45COUT1_54  = CARRY((Addr[22] & ((!\Addr[21]~43COUT1_53 ))))

	.clk(\C25M~combout ),
	.dataa(Addr[22]),
	.datab(vcc),
	.datac(\RD[6]~6 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~2_combout ),
	.ena(vcc),
	.cin(\Addr[20]~41 ),
	.cin0(\Addr[21]~43 ),
	.cin1(\Addr[21]~43COUT1_53 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[22]),
	.cout(),
	.cout0(\Addr[22]~45 ),
	.cout1(\Addr[22]~45COUT1_54 ));
// synopsys translate_off
defparam \Addr[22] .cin0_used = "true";
defparam \Addr[22] .cin1_used = "true";
defparam \Addr[22] .cin_used = "true";
defparam \Addr[22] .lut_mask = "a50a";
defparam \Addr[22] .operation_mode = "arithmetic";
defparam \Addr[22] .output_mode = "reg_only";
defparam \Addr[22] .register_cascade_mode = "off";
defparam \Addr[22] .sum_lutc_input = "cin";
defparam \Addr[22] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X7_Y4_N7
maxii_lcell \Addr[23] (
// Equation(s):
// Addr[23] = DFFEAS((Addr[23] $ (((!\Addr[20]~41  & \Addr[22]~45 ) # (\Addr[20]~41  & \Addr[22]~45COUT1_54 )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , \RD[7]~7 , , , \always9~2_combout )

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(Addr[23]),
	.datac(\RD[7]~7 ),
	.datad(vcc),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(\always9~2_combout ),
	.ena(vcc),
	.cin(\Addr[20]~41 ),
	.cin0(\Addr[22]~45 ),
	.cin1(\Addr[22]~45COUT1_54 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(Addr[23]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Addr[23] .cin0_used = "true";
defparam \Addr[23] .cin1_used = "true";
defparam \Addr[23] .cin_used = "true";
defparam \Addr[23] .lut_mask = "3c3c";
defparam \Addr[23] .operation_mode = "normal";
defparam \Addr[23] .output_mode = "reg_only";
defparam \Addr[23] .register_cascade_mode = "off";
defparam \Addr[23] .sum_lutc_input = "cin";
defparam \Addr[23] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X4_Y2_N6
maxii_lcell \SetFWr[1] (
// Equation(s):
// \RAMSpecSEL~0  = (((SetFWr[1]) # (!Addr[23])) # (!SetFWr[0]))
// SetFWr[1] = DFFEAS(\RAMSpecSEL~0 , GLOBAL(\C25M~combout ), VCC, , !\SetFWLoaded~regout , \SetFW~combout [1], , , VCC)

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(SetFWr[0]),
	.datac(\SetFW~combout [1]),
	.datad(Addr[23]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(!\SetFWLoaded~regout ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\RAMSpecSEL~0 ),
	.regout(SetFWr[1]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SetFWr[1] .lut_mask = "f3ff";
defparam \SetFWr[1] .operation_mode = "normal";
defparam \SetFWr[1] .output_mode = "reg_and_comb";
defparam \SetFWr[1] .register_cascade_mode = "off";
defparam \SetFWr[1] .sum_lutc_input = "qfbk";
defparam \SetFWr[1] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X4_Y3_N7
maxii_lcell \RAMSpecSEL~1 (
// Equation(s):
// \RAMSpecSEL~1_combout  = (\RAMRegSpecSEL~0  & (\always9~0_combout  & (\RAMSpecSEL~0  & \RAMRegSpecSEL~1 )))

	.clk(gnd),
	.dataa(\RAMRegSpecSEL~0 ),
	.datab(\always9~0_combout ),
	.datac(\RAMSpecSEL~0 ),
	.datad(\RAMRegSpecSEL~1 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\RAMSpecSEL~1_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RAMSpecSEL~1 .lut_mask = "8000";
defparam \RAMSpecSEL~1 .operation_mode = "normal";
defparam \RAMSpecSEL~1 .output_mode = "comb_only";
defparam \RAMSpecSEL~1 .register_cascade_mode = "off";
defparam \RAMSpecSEL~1 .sum_lutc_input = "datac";
defparam \RAMSpecSEL~1 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y2_N0
maxii_lcell \SA[1]~4 (
// Equation(s):
// \SA[1]~4_combout  = (PS[1]) # ((PS[0] & (!\IS.110~regout  & \RAMSpecSEL~1_combout )))

	.clk(gnd),
	.dataa(PS[0]),
	.datab(PS[1]),
	.datac(\IS.110~regout ),
	.datad(\RAMSpecSEL~1_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\SA[1]~4_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[1]~4 .lut_mask = "cecc";
defparam \SA[1]~4 .operation_mode = "normal";
defparam \SA[1]~4 .output_mode = "comb_only";
defparam \SA[1]~4 .register_cascade_mode = "off";
defparam \SA[1]~4 .sum_lutc_input = "datac";
defparam \SA[1]~4 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y3_N9
maxii_lcell \RAr[3] (
// Equation(s):
// \Mux22~1  = (\SA[1]~3_combout  & ((\SA[1]~4_combout  & ((RAr[3]))) # (!\SA[1]~4_combout  & (\Mux22~0_combout )))) # (!\SA[1]~3_combout  & (((!\SA[1]~4_combout ))))
// RAr[3] = DFFEAS(\Mux22~1 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [3], , , VCC)

	.clk(\PHI0~combout ),
	.dataa(\SA[1]~3_combout ),
	.datab(\Mux22~0_combout ),
	.datac(\RA~combout [3]),
	.datad(\SA[1]~4_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux22~1 ),
	.regout(RAr[3]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RAr[3] .lut_mask = "a0dd";
defparam \RAr[3] .operation_mode = "normal";
defparam \RAr[3] .output_mode = "reg_and_comb";
defparam \RAr[3] .register_cascade_mode = "off";
defparam \RAr[3] .sum_lutc_input = "qfbk";
defparam \RAr[3] .synch_mode = "on";
// synopsys translate_on

// Location: PIN_100,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \RA[0]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\RA~combout [0]),
	.padio(RA[0]));
// synopsys translate_off
defparam \RA[0]~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X4_Y3_N5
maxii_lcell \RAr[0] (
// Equation(s):
// \always8~0  = (RAr[1] & (RAr[2] & (RAr[0] & RAr[3])))
// RAr[0] = DFFEAS(\always8~0 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [0], , , VCC)

	.clk(\PHI0~combout ),
	.dataa(RAr[1]),
	.datab(RAr[2]),
	.datac(\RA~combout [0]),
	.datad(RAr[3]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\always8~0 ),
	.regout(RAr[0]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RAr[0] .lut_mask = "8000";
defparam \RAr[0] .operation_mode = "normal";
defparam \RAr[0] .output_mode = "reg_and_comb";
defparam \RAr[0] .register_cascade_mode = "off";
defparam \RAr[0] .sum_lutc_input = "qfbk";
defparam \RAr[0] .synch_mode = "on";
// synopsys translate_on

// Location: PIN_42,	 I/O Standard: 3.3V Schmitt Trigger Input,	 Current Strength: Default
maxii_io \nIOSTRB~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\nIOSTRB~combout ),
	.padio(nIOSTRB));
// synopsys translate_off
defparam \nIOSTRB~I .operation_mode = "input";
// synopsys translate_on

// Location: PIN_3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \RA[6]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\RA~combout [6]),
	.padio(RA[6]));
// synopsys translate_off
defparam \RA[6]~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X3_Y4_N4
maxii_lcell \RAr[6] (
// Equation(s):
// \Mux19~2  = (((RAr[6]) # (PS[0])))
// RAr[6] = DFFEAS(\Mux19~2 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [6], , , VCC)

	.clk(\PHI0~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\RA~combout [6]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux19~2 ),
	.regout(RAr[6]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RAr[6] .lut_mask = "fff0";
defparam \RAr[6] .operation_mode = "normal";
defparam \RAr[6] .output_mode = "reg_and_comb";
defparam \RAr[6] .register_cascade_mode = "off";
defparam \RAr[6] .sum_lutc_input = "qfbk";
defparam \RAr[6] .synch_mode = "on";
// synopsys translate_on

// Location: PIN_1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \RA[4]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\RA~combout [4]),
	.padio(RA[4]));
// synopsys translate_off
defparam \RA[4]~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X3_Y4_N3
maxii_lcell \RAr[4] (
// Equation(s):
// \Mux21~2  = (((RAr[4] & !PS[0])))
// RAr[4] = DFFEAS(\Mux21~2 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [4], , , VCC)

	.clk(\PHI0~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\RA~combout [4]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux21~2 ),
	.regout(RAr[4]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RAr[4] .lut_mask = "00f0";
defparam \RAr[4] .operation_mode = "normal";
defparam \RAr[4] .output_mode = "reg_and_comb";
defparam \RAr[4] .register_cascade_mode = "off";
defparam \RAr[4] .sum_lutc_input = "qfbk";
defparam \RAr[4] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X3_Y4_N2
maxii_lcell nIOSTRBr(
// Equation(s):
// \always8~1  = (((!nIOSTRBr & RAr[4])))

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\nIOSTRB~combout ),
	.datad(RAr[4]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\always8~1 ),
	.regout(\nIOSTRBr~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam nIOSTRBr.lut_mask = "0f00";
defparam nIOSTRBr.operation_mode = "normal";
defparam nIOSTRBr.output_mode = "comb_only";
defparam nIOSTRBr.register_cascade_mode = "off";
defparam nIOSTRBr.sum_lutc_input = "qfbk";
defparam nIOSTRBr.synch_mode = "on";
// synopsys translate_on

// Location: PIN_2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \RA[5]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\RA~combout [5]),
	.padio(RA[5]));
// synopsys translate_off
defparam \RA[5]~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X3_Y4_N7
maxii_lcell \RAr[5] (
// Equation(s):
// \always8~3  = (RAr[6] & (\always8~1  & (RAr[5] & \always8~2 )))
// RAr[5] = DFFEAS(\always8~3 , GLOBAL(\PHI0~combout ), VCC, , , \RA~combout [5], , , VCC)

	.clk(\PHI0~combout ),
	.dataa(RAr[6]),
	.datab(\always8~1 ),
	.datac(\RA~combout [5]),
	.datad(\always8~2 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\always8~3 ),
	.regout(RAr[5]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RAr[5] .lut_mask = "8000";
defparam \RAr[5] .operation_mode = "normal";
defparam \RAr[5] .output_mode = "reg_and_comb";
defparam \RAr[5] .register_cascade_mode = "off";
defparam \RAr[5] .sum_lutc_input = "qfbk";
defparam \RAr[5] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X4_Y1_N7
maxii_lcell \always8~4 (
// Equation(s):
// \always8~4_combout  = (\always8~0  & (\Equal19~0_combout  & (!\nIOSTRB~combout  & \always8~3 )))

	.clk(gnd),
	.dataa(\always8~0 ),
	.datab(\Equal19~0_combout ),
	.datac(\nIOSTRB~combout ),
	.datad(\always8~3 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\always8~4_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \always8~4 .lut_mask = "0800";
defparam \always8~4 .operation_mode = "normal";
defparam \always8~4 .output_mode = "comb_only";
defparam \always8~4 .register_cascade_mode = "off";
defparam \always8~4 .sum_lutc_input = "datac";
defparam \always8~4 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y1_N4
maxii_lcell IOROMEN(
// Equation(s):
// \IOROMEN~regout  = DFFEAS((!\always8~4_combout  & ((\IOROMEN~regout ) # ((\Equal19~0_combout  & !\nIOSEL~combout )))), GLOBAL(\C25M~combout ), VCC, , , , , !\nRESr~regout , )

	.clk(\C25M~combout ),
	.dataa(\IOROMEN~regout ),
	.datab(\always8~4_combout ),
	.datac(\Equal19~0_combout ),
	.datad(\nIOSEL~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(!\nRESr~regout ),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\IOROMEN~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam IOROMEN.lut_mask = "2232";
defparam IOROMEN.operation_mode = "normal";
defparam IOROMEN.output_mode = "reg_only";
defparam IOROMEN.register_cascade_mode = "off";
defparam IOROMEN.sum_lutc_input = "datac";
defparam IOROMEN.synch_mode = "on";
// synopsys translate_on

// Location: LC_X4_Y3_N2
maxii_lcell \Equal16~0 (
// Equation(s):
// \Equal16~0_combout  = (\RA~combout [2] & (\RA~combout [3] & (\RA~combout [1] & \RA~combout [0])))

	.clk(gnd),
	.dataa(\RA~combout [2]),
	.datab(\RA~combout [3]),
	.datac(\RA~combout [1]),
	.datad(\RA~combout [0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Equal16~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Equal16~0 .lut_mask = "8000";
defparam \Equal16~0 .operation_mode = "normal";
defparam \Equal16~0 .output_mode = "comb_only";
defparam \Equal16~0 .register_cascade_mode = "off";
defparam \Equal16~0 .sum_lutc_input = "datac";
defparam \Equal16~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y4_N1
maxii_lcell \Equal16~1 (
// Equation(s):
// \Equal16~1_combout  = (\RA~combout [4] & (\RA~combout [7] & (\RA~combout [6] & \RA~combout [5])))

	.clk(gnd),
	.dataa(\RA~combout [4]),
	.datab(\RA~combout [7]),
	.datac(\RA~combout [6]),
	.datad(\RA~combout [5]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Equal16~1_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Equal16~1 .lut_mask = "8000";
defparam \Equal16~1 .operation_mode = "normal";
defparam \Equal16~1 .output_mode = "comb_only";
defparam \Equal16~1 .register_cascade_mode = "off";
defparam \Equal16~1 .sum_lutc_input = "datac";
defparam \Equal16~1 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y2_N1
maxii_lcell \Equal16~2 (
// Equation(s):
// \Equal16~2_combout  = (\RA~combout [9] & (\RA~combout [8] & (\RA~combout [10] & \Equal16~1_combout )))

	.clk(gnd),
	.dataa(\RA~combout [9]),
	.datab(\RA~combout [8]),
	.datac(\RA~combout [10]),
	.datad(\Equal16~1_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Equal16~2_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Equal16~2 .lut_mask = "8000";
defparam \Equal16~2 .operation_mode = "normal";
defparam \Equal16~2 .output_mode = "comb_only";
defparam \Equal16~2 .register_cascade_mode = "off";
defparam \Equal16~2 .sum_lutc_input = "datac";
defparam \Equal16~2 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y1_N3
maxii_lcell \comb~1 (
// Equation(s):
// \comb~1_combout  = (\IOROMEN~regout  & (!\nIOSTRB~combout  & ((!\Equal16~2_combout ) # (!\Equal16~0_combout ))))

	.clk(gnd),
	.dataa(\IOROMEN~regout ),
	.datab(\Equal16~0_combout ),
	.datac(\nIOSTRB~combout ),
	.datad(\Equal16~2_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\comb~1_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \comb~1 .lut_mask = "020a";
defparam \comb~1 .operation_mode = "normal";
defparam \comb~1 .output_mode = "comb_only";
defparam \comb~1 .register_cascade_mode = "off";
defparam \comb~1 .sum_lutc_input = "datac";
defparam \comb~1 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y1_N8
maxii_lcell \comb~2 (
// Equation(s):
// \comb~2_combout  = (\comb~0  & ((\comb~1_combout ) # ((!\nDEVSEL~combout ) # (!\nIOSEL~combout ))))

	.clk(gnd),
	.dataa(\comb~1_combout ),
	.datab(\nIOSEL~combout ),
	.datac(\nDEVSEL~combout ),
	.datad(\comb~0 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\comb~2_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \comb~2 .lut_mask = "bf00";
defparam \comb~2 .operation_mode = "normal";
defparam \comb~2 .output_mode = "comb_only";
defparam \comb~2 .register_cascade_mode = "off";
defparam \comb~2 .sum_lutc_input = "datac";
defparam \comb~2 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y2_N1
maxii_lcell \Mux14~2 (
// Equation(s):
// \Mux14~2_combout  = (((PS[1]) # (PS[0])))

	.clk(gnd),
	.dataa(vcc),
	.datab(vcc),
	.datac(PS[1]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux14~2_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux14~2 .lut_mask = "fff0";
defparam \Mux14~2 .operation_mode = "normal";
defparam \Mux14~2 .output_mode = "comb_only";
defparam \Mux14~2 .register_cascade_mode = "off";
defparam \Mux14~2 .sum_lutc_input = "datac";
defparam \Mux14~2 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y2_N7
maxii_lcell \Mux14~3 (
// Equation(s):
// \Mux14~3_combout  = (Addr[23] & (!SetFWr[1] & (!\IS.110~regout  & !\Mux14~2_combout )))

	.clk(gnd),
	.dataa(Addr[23]),
	.datab(SetFWr[1]),
	.datac(\IS.110~regout ),
	.datad(\Mux14~2_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux14~3_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux14~3 .lut_mask = "0002";
defparam \Mux14~3 .operation_mode = "normal";
defparam \Mux14~3 .output_mode = "comb_only";
defparam \Mux14~3 .register_cascade_mode = "off";
defparam \Mux14~3 .sum_lutc_input = "datac";
defparam \Mux14~3 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y2_N8
maxii_lcell \Mux14~0 (
// Equation(s):
// \Mux14~0_combout  = (Addr[23] & (!SetFWr[1] & (PS[1] $ (PS[0]))))

	.clk(gnd),
	.dataa(Addr[23]),
	.datab(SetFWr[1]),
	.datac(PS[1]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux14~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux14~0 .lut_mask = "0220";
defparam \Mux14~0 .operation_mode = "normal";
defparam \Mux14~0 .output_mode = "comb_only";
defparam \Mux14~0 .register_cascade_mode = "off";
defparam \Mux14~0 .sum_lutc_input = "datac";
defparam \Mux14~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y2_N9
maxii_lcell \Mux14~1 (
// Equation(s):
// \Mux14~1_combout  = (\RAMSpecSEL~1_combout  & (\Mux14~0_combout  & ((PS[1]) # (!\IS.110~regout ))))

	.clk(gnd),
	.dataa(PS[1]),
	.datab(\RAMSpecSEL~1_combout ),
	.datac(\IS.110~regout ),
	.datad(\Mux14~0_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux14~1_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux14~1 .lut_mask = "8c00";
defparam \Mux14~1 .operation_mode = "normal";
defparam \Mux14~1 .output_mode = "comb_only";
defparam \Mux14~1 .register_cascade_mode = "off";
defparam \Mux14~1 .sum_lutc_input = "datac";
defparam \Mux14~1 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y2_N0
maxii_lcell \SBA[0]~reg0 (
// Equation(s):
// \SBA[0]~reg0_regout  = DFFEAS(((PS[3] & (\Mux14~3_combout )) # (!PS[3] & ((\Mux14~1_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , PS[2], )

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(\Mux14~3_combout ),
	.datac(PS[3]),
	.datad(\Mux14~1_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(PS[2]),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SBA[0]~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SBA[0]~reg0 .lut_mask = "cfc0";
defparam \SBA[0]~reg0 .operation_mode = "normal";
defparam \SBA[0]~reg0 .output_mode = "reg_only";
defparam \SBA[0]~reg0 .register_cascade_mode = "off";
defparam \SBA[0]~reg0 .sum_lutc_input = "datac";
defparam \SBA[0]~reg0 .synch_mode = "on";
// synopsys translate_on

// Location: LC_X4_Y2_N5
maxii_lcell \Mux13~0 (
// Equation(s):
// \Mux13~0_combout  = (PS[0] & (!PS[1] & ((\IS.110~regout ) # (!\RAMSpecSEL~1_combout )))) # (!PS[0] & (PS[1] & ((!\RAMSpecSEL~1_combout ))))

	.clk(gnd),
	.dataa(PS[0]),
	.datab(PS[1]),
	.datac(\IS.110~regout ),
	.datad(\RAMSpecSEL~1_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux13~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux13~0 .lut_mask = "2066";
defparam \Mux13~0 .operation_mode = "normal";
defparam \Mux13~0 .output_mode = "comb_only";
defparam \Mux13~0 .register_cascade_mode = "off";
defparam \Mux13~0 .sum_lutc_input = "datac";
defparam \Mux13~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y2_N8
maxii_lcell \SBA[1]~reg0 (
// Equation(s):
// \SBA[1]~reg0_regout  = DFFEAS((PS[3] & (\IS.110~regout  & ((!\Mux14~2_combout )))) # (!PS[3] & (((\Mux13~0_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , PS[2], )

	.clk(\C25M~combout ),
	.dataa(\IS.110~regout ),
	.datab(\Mux13~0_combout ),
	.datac(PS[3]),
	.datad(\Mux14~2_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(PS[2]),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SBA[1]~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SBA[1]~reg0 .lut_mask = "0cac";
defparam \SBA[1]~reg0 .operation_mode = "normal";
defparam \SBA[1]~reg0 .output_mode = "reg_only";
defparam \SBA[1]~reg0 .register_cascade_mode = "off";
defparam \SBA[1]~reg0 .sum_lutc_input = "datac";
defparam \SBA[1]~reg0 .synch_mode = "on";
// synopsys translate_on

// Location: LC_X6_Y2_N7
maxii_lcell \Mux24~3 (
// Equation(s):
// \Mux24~3_combout  = (PS[3] & (LS[1] & ((!\Mux14~2_combout )))) # (!PS[3] & (((\Mux24~2 ))))

	.clk(gnd),
	.dataa(PS[3]),
	.datab(LS[1]),
	.datac(\Mux24~2 ),
	.datad(\Mux14~2_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux24~3_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux24~3 .lut_mask = "50d8";
defparam \Mux24~3 .operation_mode = "normal";
defparam \Mux24~3 .output_mode = "comb_only";
defparam \Mux24~3 .register_cascade_mode = "off";
defparam \Mux24~3 .sum_lutc_input = "datac";
defparam \Mux24~3 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y4_N4
maxii_lcell \SA[1]~5 (
// Equation(s):
// \SA[1]~5_combout  = ((PS[0]) # ((\IS.110~regout  & PS[3])))

	.clk(gnd),
	.dataa(vcc),
	.datab(\IS.110~regout ),
	.datac(PS[3]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\SA[1]~5_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[1]~5 .lut_mask = "ffc0";
defparam \SA[1]~5 .operation_mode = "normal";
defparam \SA[1]~5 .output_mode = "comb_only";
defparam \SA[1]~5 .register_cascade_mode = "off";
defparam \SA[1]~5 .sum_lutc_input = "datac";
defparam \SA[1]~5 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y4_N7
maxii_lcell \SA[1]~6 (
// Equation(s):
// \SA[1]~6_combout  = (\SA[1]~5_combout ) # ((PS[1] & ((PS[3]) # (!\RAMSpecSEL~1_combout ))) # (!PS[1] & (!PS[3])))

	.clk(gnd),
	.dataa(\SA[1]~5_combout ),
	.datab(PS[1]),
	.datac(PS[3]),
	.datad(\RAMSpecSEL~1_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\SA[1]~6_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[1]~6 .lut_mask = "ebef";
defparam \SA[1]~6 .operation_mode = "normal";
defparam \SA[1]~6 .output_mode = "comb_only";
defparam \SA[1]~6 .register_cascade_mode = "off";
defparam \SA[1]~6 .sum_lutc_input = "datac";
defparam \SA[1]~6 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y2_N5
maxii_lcell \SA[0]~reg0 (
// Equation(s):
// \SA[0]~reg0_regout  = DFFEAS(((\SA[1]~6_combout  & ((\Mux24~3_combout ))) # (!\SA[1]~6_combout  & (Addr[1]))), GLOBAL(\C25M~combout ), VCC, , , , , PS[2], )

	.clk(\C25M~combout ),
	.dataa(Addr[1]),
	.datab(vcc),
	.datac(\Mux24~3_combout ),
	.datad(\SA[1]~6_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(PS[2]),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SA[0]~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[0]~reg0 .lut_mask = "f0aa";
defparam \SA[0]~reg0 .operation_mode = "normal";
defparam \SA[0]~reg0 .output_mode = "reg_only";
defparam \SA[0]~reg0 .register_cascade_mode = "off";
defparam \SA[0]~reg0 .sum_lutc_input = "datac";
defparam \SA[0]~reg0 .synch_mode = "on";
// synopsys translate_on

// Location: LC_X6_Y2_N6
maxii_lcell \Mux23~3 (
// Equation(s):
// \Mux23~3_combout  = (PS[3] & (!\Mux14~2_combout  & (LS[2]))) # (!PS[3] & (((\Mux23~2 ))))

	.clk(gnd),
	.dataa(\Mux14~2_combout ),
	.datab(LS[2]),
	.datac(PS[3]),
	.datad(\Mux23~2 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux23~3_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux23~3 .lut_mask = "4f40";
defparam \Mux23~3 .operation_mode = "normal";
defparam \Mux23~3 .output_mode = "comb_only";
defparam \Mux23~3 .register_cascade_mode = "off";
defparam \Mux23~3 .sum_lutc_input = "datac";
defparam \Mux23~3 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y2_N4
maxii_lcell \SA[1]~reg0 (
// Equation(s):
// \SA[1]~reg0_regout  = DFFEAS(((\SA[1]~6_combout  & ((\Mux23~3_combout ))) # (!\SA[1]~6_combout  & (Addr[2]))), GLOBAL(\C25M~combout ), VCC, , , , , PS[2], )

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(Addr[2]),
	.datac(\Mux23~3_combout ),
	.datad(\SA[1]~6_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(PS[2]),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SA[1]~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[1]~reg0 .lut_mask = "f0cc";
defparam \SA[1]~reg0 .operation_mode = "normal";
defparam \SA[1]~reg0 .output_mode = "reg_only";
defparam \SA[1]~reg0 .register_cascade_mode = "off";
defparam \SA[1]~reg0 .sum_lutc_input = "datac";
defparam \SA[1]~reg0 .synch_mode = "on";
// synopsys translate_on

// Location: LC_X6_Y2_N9
maxii_lcell Bank(
// Equation(s):
// \Bank~regout  = DFFEAS((\always9~1_combout  & ((\always8~0  & (\RD[0]~0 )) # (!\always8~0  & ((\Bank~regout ))))) # (!\always9~1_combout  & (((\Bank~regout )))), GLOBAL(\C25M~combout ), GLOBAL(\nRESr~regout ), , , , , , )

	.clk(\C25M~combout ),
	.dataa(\always9~1_combout ),
	.datab(\RD[0]~0 ),
	.datac(\always8~0 ),
	.datad(\Bank~regout ),
	.aclr(!\nRESr~regout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\Bank~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam Bank.lut_mask = "df80";
defparam Bank.operation_mode = "normal";
defparam Bank.output_mode = "reg_only";
defparam Bank.register_cascade_mode = "off";
defparam Bank.sum_lutc_input = "datac";
defparam Bank.synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y2_N3
maxii_lcell \Mux22~2 (
// Equation(s):
// \Mux22~2_combout  = (\SA[1]~2_combout  & (((\Mux22~1 )))) # (!\SA[1]~2_combout  & ((\Mux22~1  & ((\Bank~regout ))) # (!\Mux22~1  & (Addr[12]))))

	.clk(gnd),
	.dataa(Addr[12]),
	.datab(\SA[1]~2_combout ),
	.datac(\Mux22~1 ),
	.datad(\Bank~regout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux22~2_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux22~2 .lut_mask = "f2c2";
defparam \Mux22~2 .operation_mode = "normal";
defparam \Mux22~2 .output_mode = "comb_only";
defparam \Mux22~2 .register_cascade_mode = "off";
defparam \Mux22~2 .sum_lutc_input = "datac";
defparam \Mux22~2 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y2_N0
maxii_lcell \Mux22~3 (
// Equation(s):
// \Mux22~3_combout  = (PS[3] & (((LS[3] & !\Mux14~2_combout )))) # (!PS[3] & (\Mux22~2_combout ))

	.clk(gnd),
	.dataa(\Mux22~2_combout ),
	.datab(LS[3]),
	.datac(PS[3]),
	.datad(\Mux14~2_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux22~3_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux22~3 .lut_mask = "0aca";
defparam \Mux22~3 .operation_mode = "normal";
defparam \Mux22~3 .output_mode = "comb_only";
defparam \Mux22~3 .register_cascade_mode = "off";
defparam \Mux22~3 .sum_lutc_input = "datac";
defparam \Mux22~3 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y2_N1
maxii_lcell \SA[2]~reg0 (
// Equation(s):
// \SA[2]~reg0_regout  = DFFEAS(((\SA[1]~6_combout  & ((\Mux22~3_combout ))) # (!\SA[1]~6_combout  & (Addr[3]))), GLOBAL(\C25M~combout ), VCC, , , , , PS[2], )

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(Addr[3]),
	.datac(\Mux22~3_combout ),
	.datad(\SA[1]~6_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(PS[2]),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SA[2]~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[2]~reg0 .lut_mask = "f0cc";
defparam \SA[2]~reg0 .operation_mode = "normal";
defparam \SA[2]~reg0 .output_mode = "reg_only";
defparam \SA[2]~reg0 .register_cascade_mode = "off";
defparam \SA[2]~reg0 .sum_lutc_input = "datac";
defparam \SA[2]~reg0 .synch_mode = "on";
// synopsys translate_on

// Location: LC_X6_Y4_N6
maxii_lcell \SA[3]~15 (
// Equation(s):
// \SA[3]~15_combout  = (PS[3] & (!PS[1] & (!\IS.110~regout  & !PS[0]))) # (!PS[3] & (PS[1]))

	.clk(gnd),
	.dataa(PS[3]),
	.datab(PS[1]),
	.datac(\IS.110~regout ),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\SA[3]~15_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[3]~15 .lut_mask = "4446";
defparam \SA[3]~15 .operation_mode = "normal";
defparam \SA[3]~15 .output_mode = "comb_only";
defparam \SA[3]~15 .register_cascade_mode = "off";
defparam \SA[3]~15 .sum_lutc_input = "datac";
defparam \SA[3]~15 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y4_N8
maxii_lcell \SA[3]~9 (
// Equation(s):
// \SA[3]~9_combout  = ((PS[3] & (!PS[1] & !PS[0]))) # (!\SA[1]~6_combout )

	.clk(gnd),
	.dataa(PS[3]),
	.datab(PS[1]),
	.datac(\SA[1]~6_combout ),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\SA[3]~9_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[3]~9 .lut_mask = "0f2f";
defparam \SA[3]~9 .operation_mode = "normal";
defparam \SA[3]~9 .output_mode = "comb_only";
defparam \SA[3]~9 .register_cascade_mode = "off";
defparam \SA[3]~9 .sum_lutc_input = "datac";
defparam \SA[3]~9 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y4_N6
maxii_lcell \Mux21~3 (
// Equation(s):
// \Mux21~3_combout  = (\SA[3]~15_combout  & (((Addr[4]) # (!\SA[3]~9_combout )))) # (!\SA[3]~15_combout  & (LS[4] & ((\SA[3]~9_combout ))))

	.clk(gnd),
	.dataa(\SA[3]~15_combout ),
	.datab(LS[4]),
	.datac(Addr[4]),
	.datad(\SA[3]~9_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux21~3_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux21~3 .lut_mask = "e4aa";
defparam \Mux21~3 .operation_mode = "normal";
defparam \Mux21~3 .output_mode = "comb_only";
defparam \Mux21~3 .register_cascade_mode = "off";
defparam \Mux21~3 .sum_lutc_input = "datac";
defparam \Mux21~3 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y4_N8
maxii_lcell \Mux21~4 (
// Equation(s):
// \Mux21~4_combout  = (Addr[13] & (PS[0] & (\RAMSpecSEL~1_combout  & !\IS.110~regout )))

	.clk(gnd),
	.dataa(Addr[13]),
	.datab(PS[0]),
	.datac(\RAMSpecSEL~1_combout ),
	.datad(\IS.110~regout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux21~4_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux21~4 .lut_mask = "0080";
defparam \Mux21~4 .operation_mode = "normal";
defparam \Mux21~4 .output_mode = "comb_only";
defparam \Mux21~4 .register_cascade_mode = "off";
defparam \Mux21~4 .sum_lutc_input = "datac";
defparam \Mux21~4 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y4_N2
maxii_lcell \SA[3]~8 (
// Equation(s):
// \SA[3]~8_combout  = (PS[3]) # ((!\SA[1]~5_combout  & (PS[1] & \RAMSpecSEL~1_combout )))

	.clk(gnd),
	.dataa(\SA[1]~5_combout ),
	.datab(PS[1]),
	.datac(PS[3]),
	.datad(\RAMSpecSEL~1_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\SA[3]~8_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[3]~8 .lut_mask = "f4f0";
defparam \SA[3]~8 .operation_mode = "normal";
defparam \SA[3]~8 .output_mode = "comb_only";
defparam \SA[3]~8 .register_cascade_mode = "off";
defparam \SA[3]~8 .sum_lutc_input = "datac";
defparam \SA[3]~8 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y4_N3
maxii_lcell \SA[3]~reg0 (
// Equation(s):
// \SA[3]~reg0_regout  = DFFEAS((\Mux21~3_combout  & ((\Mux21~2 ) # ((\SA[3]~8_combout )))) # (!\Mux21~3_combout  & (((\Mux21~4_combout  & !\SA[3]~8_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , PS[2], )

	.clk(\C25M~combout ),
	.dataa(\Mux21~3_combout ),
	.datab(\Mux21~2 ),
	.datac(\Mux21~4_combout ),
	.datad(\SA[3]~8_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(PS[2]),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SA[3]~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[3]~reg0 .lut_mask = "aad8";
defparam \SA[3]~reg0 .operation_mode = "normal";
defparam \SA[3]~reg0 .output_mode = "reg_only";
defparam \SA[3]~reg0 .register_cascade_mode = "off";
defparam \SA[3]~reg0 .sum_lutc_input = "datac";
defparam \SA[3]~reg0 .synch_mode = "on";
// synopsys translate_on

// Location: LC_X3_Y4_N9
maxii_lcell \Mux20~4 (
// Equation(s):
// \Mux20~4_combout  = (\RAMSpecSEL~1_combout  & (PS[0] & (Addr[14] & !\IS.110~regout )))

	.clk(gnd),
	.dataa(\RAMSpecSEL~1_combout ),
	.datab(PS[0]),
	.datac(Addr[14]),
	.datad(\IS.110~regout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux20~4_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux20~4 .lut_mask = "0080";
defparam \Mux20~4 .operation_mode = "normal";
defparam \Mux20~4 .output_mode = "comb_only";
defparam \Mux20~4 .register_cascade_mode = "off";
defparam \Mux20~4 .sum_lutc_input = "datac";
defparam \Mux20~4 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y4_N0
maxii_lcell \Mux20~2 (
// Equation(s):
// \Mux20~2_combout  = (RAr[5] & (((!PS[0]))))

	.clk(gnd),
	.dataa(RAr[5]),
	.datab(vcc),
	.datac(vcc),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux20~2_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux20~2 .lut_mask = "00aa";
defparam \Mux20~2 .operation_mode = "normal";
defparam \Mux20~2 .output_mode = "comb_only";
defparam \Mux20~2 .register_cascade_mode = "off";
defparam \Mux20~2 .sum_lutc_input = "datac";
defparam \Mux20~2 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y4_N7
maxii_lcell \Mux20~3 (
// Equation(s):
// \Mux20~3_combout  = (\SA[3]~9_combout  & ((\SA[3]~15_combout  & ((Addr[5]))) # (!\SA[3]~15_combout  & (LS[5])))) # (!\SA[3]~9_combout  & (((\SA[3]~15_combout ))))

	.clk(gnd),
	.dataa(LS[5]),
	.datab(\SA[3]~9_combout ),
	.datac(\SA[3]~15_combout ),
	.datad(Addr[5]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux20~3_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux20~3 .lut_mask = "f838";
defparam \Mux20~3 .operation_mode = "normal";
defparam \Mux20~3 .output_mode = "comb_only";
defparam \Mux20~3 .register_cascade_mode = "off";
defparam \Mux20~3 .sum_lutc_input = "datac";
defparam \Mux20~3 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y4_N4
maxii_lcell \SA[4]~reg0 (
// Equation(s):
// \SA[4]~reg0_regout  = DFFEAS((\Mux20~3_combout  & (((\Mux20~2_combout ) # (\SA[3]~8_combout )))) # (!\Mux20~3_combout  & (\Mux20~4_combout  & ((!\SA[3]~8_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , PS[2], )

	.clk(\C25M~combout ),
	.dataa(\Mux20~4_combout ),
	.datab(\Mux20~2_combout ),
	.datac(\Mux20~3_combout ),
	.datad(\SA[3]~8_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(PS[2]),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SA[4]~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[4]~reg0 .lut_mask = "f0ca";
defparam \SA[4]~reg0 .operation_mode = "normal";
defparam \SA[4]~reg0 .output_mode = "reg_only";
defparam \SA[4]~reg0 .register_cascade_mode = "off";
defparam \SA[4]~reg0 .sum_lutc_input = "datac";
defparam \SA[4]~reg0 .synch_mode = "on";
// synopsys translate_on

// Location: LC_X6_Y4_N5
maxii_lcell \Mux19~3 (
// Equation(s):
// \Mux19~3_combout  = (\SA[3]~15_combout  & (Addr[6] & ((\SA[3]~9_combout )))) # (!\SA[3]~15_combout  & (((LS[6]) # (!\SA[3]~9_combout ))))

	.clk(gnd),
	.dataa(Addr[6]),
	.datab(\SA[3]~15_combout ),
	.datac(LS[6]),
	.datad(\SA[3]~9_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux19~3_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux19~3 .lut_mask = "b833";
defparam \Mux19~3 .operation_mode = "normal";
defparam \Mux19~3 .output_mode = "comb_only";
defparam \Mux19~3 .register_cascade_mode = "off";
defparam \Mux19~3 .sum_lutc_input = "datac";
defparam \Mux19~3 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y4_N9
maxii_lcell \Mux19~5 (
// Equation(s):
// \Mux19~5_combout  = (\IS.110~regout ) # (((Addr[15]) # (!PS[0])) # (!\RAMSpecSEL~1_combout ))

	.clk(gnd),
	.dataa(\IS.110~regout ),
	.datab(\RAMSpecSEL~1_combout ),
	.datac(Addr[15]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux19~5_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux19~5 .lut_mask = "fbff";
defparam \Mux19~5 .operation_mode = "normal";
defparam \Mux19~5 .output_mode = "comb_only";
defparam \Mux19~5 .register_cascade_mode = "off";
defparam \Mux19~5 .sum_lutc_input = "datac";
defparam \Mux19~5 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y4_N3
maxii_lcell \Mux19~4 (
// Equation(s):
// \Mux19~4_combout  = (\Mux19~3_combout  & ((\Mux19~5_combout ) # ((\SA[3]~8_combout )))) # (!\Mux19~3_combout  & (((\Mux19~2  & !\SA[3]~8_combout ))))

	.clk(gnd),
	.dataa(\Mux19~3_combout ),
	.datab(\Mux19~5_combout ),
	.datac(\Mux19~2 ),
	.datad(\SA[3]~8_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux19~4_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux19~4 .lut_mask = "aad8";
defparam \Mux19~4 .operation_mode = "normal";
defparam \Mux19~4 .output_mode = "comb_only";
defparam \Mux19~4 .register_cascade_mode = "off";
defparam \Mux19~4 .sum_lutc_input = "datac";
defparam \Mux19~4 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y4_N1
maxii_lcell \SA[5]~reg0 (
// Equation(s):
// \SA[5]~reg0_regout  = DFFEAS((((\Mux19~4_combout ))), GLOBAL(\C25M~combout ), VCC, , , VCC, , , PS[2])

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\Mux19~4_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(PS[2]),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SA[5]~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[5]~reg0 .lut_mask = "ff00";
defparam \SA[5]~reg0 .operation_mode = "normal";
defparam \SA[5]~reg0 .output_mode = "reg_only";
defparam \SA[5]~reg0 .register_cascade_mode = "off";
defparam \SA[5]~reg0 .sum_lutc_input = "datac";
defparam \SA[5]~reg0 .synch_mode = "on";
// synopsys translate_on

// Location: LC_X3_Y4_N0
maxii_lcell \Mux18~4 (
// Equation(s):
// \Mux18~4_combout  = (!\IS.110~regout  & (PS[0] & (\RAMSpecSEL~1_combout  & Addr[16])))

	.clk(gnd),
	.dataa(\IS.110~regout ),
	.datab(PS[0]),
	.datac(\RAMSpecSEL~1_combout ),
	.datad(Addr[16]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux18~4_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux18~4 .lut_mask = "4000";
defparam \Mux18~4 .operation_mode = "normal";
defparam \Mux18~4 .output_mode = "comb_only";
defparam \Mux18~4 .register_cascade_mode = "off";
defparam \Mux18~4 .sum_lutc_input = "datac";
defparam \Mux18~4 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y4_N0
maxii_lcell \Mux18~3 (
// Equation(s):
// \Mux18~3_combout  = (\SA[3]~15_combout  & ((Addr[7]) # ((!\SA[3]~9_combout )))) # (!\SA[3]~15_combout  & (((LS[7] & \SA[3]~9_combout ))))

	.clk(gnd),
	.dataa(\SA[3]~15_combout ),
	.datab(Addr[7]),
	.datac(LS[7]),
	.datad(\SA[3]~9_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux18~3_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux18~3 .lut_mask = "d8aa";
defparam \Mux18~3 .operation_mode = "normal";
defparam \Mux18~3 .output_mode = "comb_only";
defparam \Mux18~3 .register_cascade_mode = "off";
defparam \Mux18~3 .sum_lutc_input = "datac";
defparam \Mux18~3 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y2_N9
maxii_lcell \Mux18~2 (
// Equation(s):
// \Mux18~2_combout  = (((RAr[7] & !PS[0])))

	.clk(gnd),
	.dataa(vcc),
	.datab(vcc),
	.datac(RAr[7]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux18~2_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux18~2 .lut_mask = "00f0";
defparam \Mux18~2 .operation_mode = "normal";
defparam \Mux18~2 .output_mode = "comb_only";
defparam \Mux18~2 .register_cascade_mode = "off";
defparam \Mux18~2 .sum_lutc_input = "datac";
defparam \Mux18~2 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y4_N8
maxii_lcell \SA[6]~reg0 (
// Equation(s):
// \SA[6]~reg0_regout  = DFFEAS((\SA[3]~8_combout  & (((\Mux18~3_combout )))) # (!\SA[3]~8_combout  & ((\Mux18~3_combout  & ((\Mux18~2_combout ))) # (!\Mux18~3_combout  & (\Mux18~4_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , PS[2], )

	.clk(\C25M~combout ),
	.dataa(\Mux18~4_combout ),
	.datab(\SA[3]~8_combout ),
	.datac(\Mux18~3_combout ),
	.datad(\Mux18~2_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(PS[2]),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SA[6]~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[6]~reg0 .lut_mask = "f2c2";
defparam \SA[6]~reg0 .operation_mode = "normal";
defparam \SA[6]~reg0 .output_mode = "reg_only";
defparam \SA[6]~reg0 .register_cascade_mode = "off";
defparam \SA[6]~reg0 .sum_lutc_input = "datac";
defparam \SA[6]~reg0 .synch_mode = "on";
// synopsys translate_on

// Location: LC_X3_Y4_N5
maxii_lcell \Mux17~4 (
// Equation(s):
// \Mux17~4_combout  = (Addr[17] & (PS[0] & (\RAMSpecSEL~1_combout  & !\IS.110~regout )))

	.clk(gnd),
	.dataa(Addr[17]),
	.datab(PS[0]),
	.datac(\RAMSpecSEL~1_combout ),
	.datad(\IS.110~regout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux17~4_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux17~4 .lut_mask = "0080";
defparam \Mux17~4 .operation_mode = "normal";
defparam \Mux17~4 .output_mode = "comb_only";
defparam \Mux17~4 .register_cascade_mode = "off";
defparam \Mux17~4 .sum_lutc_input = "datac";
defparam \Mux17~4 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y2_N5
maxii_lcell \Mux17~2 (
// Equation(s):
// \Mux17~2_combout  = (((RAr[8] & !PS[0])))

	.clk(gnd),
	.dataa(vcc),
	.datab(vcc),
	.datac(RAr[8]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux17~2_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux17~2 .lut_mask = "00f0";
defparam \Mux17~2 .operation_mode = "normal";
defparam \Mux17~2 .output_mode = "comb_only";
defparam \Mux17~2 .register_cascade_mode = "off";
defparam \Mux17~2 .sum_lutc_input = "datac";
defparam \Mux17~2 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y4_N2
maxii_lcell \Mux17~3 (
// Equation(s):
// \Mux17~3_combout  = (\SA[3]~15_combout  & ((Addr[8]) # ((!\SA[3]~9_combout )))) # (!\SA[3]~15_combout  & (((LS[8] & \SA[3]~9_combout ))))

	.clk(gnd),
	.dataa(Addr[8]),
	.datab(LS[8]),
	.datac(\SA[3]~15_combout ),
	.datad(\SA[3]~9_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux17~3_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux17~3 .lut_mask = "acf0";
defparam \Mux17~3 .operation_mode = "normal";
defparam \Mux17~3 .output_mode = "comb_only";
defparam \Mux17~3 .register_cascade_mode = "off";
defparam \Mux17~3 .sum_lutc_input = "datac";
defparam \Mux17~3 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y4_N9
maxii_lcell \SA[7]~reg0 (
// Equation(s):
// \SA[7]~reg0_regout  = DFFEAS((\SA[3]~8_combout  & (((\Mux17~3_combout )))) # (!\SA[3]~8_combout  & ((\Mux17~3_combout  & ((\Mux17~2_combout ))) # (!\Mux17~3_combout  & (\Mux17~4_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , PS[2], )

	.clk(\C25M~combout ),
	.dataa(\Mux17~4_combout ),
	.datab(\SA[3]~8_combout ),
	.datac(\Mux17~2_combout ),
	.datad(\Mux17~3_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(PS[2]),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SA[7]~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[7]~reg0 .lut_mask = "fc22";
defparam \SA[7]~reg0 .operation_mode = "normal";
defparam \SA[7]~reg0 .output_mode = "reg_only";
defparam \SA[7]~reg0 .register_cascade_mode = "off";
defparam \SA[7]~reg0 .sum_lutc_input = "datac";
defparam \SA[7]~reg0 .synch_mode = "on";
// synopsys translate_on

// Location: LC_X4_Y4_N5
maxii_lcell \Mux16~3 (
// Equation(s):
// \Mux16~3_combout  = (\SA[3]~15_combout  & ((Addr[9]) # ((!\SA[3]~9_combout )))) # (!\SA[3]~15_combout  & (((LS[9] & \SA[3]~9_combout ))))

	.clk(gnd),
	.dataa(Addr[9]),
	.datab(LS[9]),
	.datac(\SA[3]~15_combout ),
	.datad(\SA[3]~9_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux16~3_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux16~3 .lut_mask = "acf0";
defparam \Mux16~3 .operation_mode = "normal";
defparam \Mux16~3 .output_mode = "comb_only";
defparam \Mux16~3 .register_cascade_mode = "off";
defparam \Mux16~3 .sum_lutc_input = "datac";
defparam \Mux16~3 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y4_N6
maxii_lcell \Mux16~4 (
// Equation(s):
// \Mux16~4_combout  = (Addr[18] & (PS[0] & (\RAMSpecSEL~1_combout  & !\IS.110~regout )))

	.clk(gnd),
	.dataa(Addr[18]),
	.datab(PS[0]),
	.datac(\RAMSpecSEL~1_combout ),
	.datad(\IS.110~regout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux16~4_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux16~4 .lut_mask = "0080";
defparam \Mux16~4 .operation_mode = "normal";
defparam \Mux16~4 .output_mode = "comb_only";
defparam \Mux16~4 .register_cascade_mode = "off";
defparam \Mux16~4 .sum_lutc_input = "datac";
defparam \Mux16~4 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y4_N1
maxii_lcell \SA[8]~reg0 (
// Equation(s):
// \SA[8]~reg0_regout  = DFFEAS((\Mux16~3_combout  & (((\Mux16~2 ) # (\SA[3]~8_combout )))) # (!\Mux16~3_combout  & (\Mux16~4_combout  & ((!\SA[3]~8_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , PS[2], )

	.clk(\C25M~combout ),
	.dataa(\Mux16~3_combout ),
	.datab(\Mux16~4_combout ),
	.datac(\Mux16~2 ),
	.datad(\SA[3]~8_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(PS[2]),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SA[8]~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[8]~reg0 .lut_mask = "aae4";
defparam \SA[8]~reg0 .operation_mode = "normal";
defparam \SA[8]~reg0 .output_mode = "reg_only";
defparam \SA[8]~reg0 .register_cascade_mode = "off";
defparam \SA[8]~reg0 .sum_lutc_input = "datac";
defparam \SA[8]~reg0 .synch_mode = "on";
// synopsys translate_on

// Location: LC_X7_Y1_N0
maxii_lcell \SA[1]~7 (
// Equation(s):
// \SA[1]~7_combout  = (PS[0] & (((!\IS.110~regout ))))

	.clk(gnd),
	.dataa(PS[0]),
	.datab(vcc),
	.datac(vcc),
	.datad(\IS.110~regout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\SA[1]~7_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[1]~7 .lut_mask = "00aa";
defparam \SA[1]~7 .operation_mode = "normal";
defparam \SA[1]~7 .output_mode = "comb_only";
defparam \SA[1]~7 .register_cascade_mode = "off";
defparam \SA[1]~7 .sum_lutc_input = "datac";
defparam \SA[1]~7 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y2_N5
maxii_lcell \SA~10 (
// Equation(s):
// \SA~10_combout  = (\SA[1]~7_combout  & (\RAMSpecSEL~1_combout  & (!PS[2] & \Equal1~0_combout )))

	.clk(gnd),
	.dataa(\SA[1]~7_combout ),
	.datab(\RAMSpecSEL~1_combout ),
	.datac(PS[2]),
	.datad(\Equal1~0_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\SA~10_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA~10 .lut_mask = "0800";
defparam \SA~10 .operation_mode = "normal";
defparam \SA~10 .output_mode = "comb_only";
defparam \SA~10 .register_cascade_mode = "off";
defparam \SA~10 .sum_lutc_input = "datac";
defparam \SA~10 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y4_N9
maxii_lcell \SA[9]~reg0 (
// Equation(s):
// \SA[9]~reg0_regout  = DFFEAS((((Addr[19])) # (!\SA~10_combout )), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(\SA~10_combout ),
	.datac(vcc),
	.datad(Addr[19]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SA[9]~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[9]~reg0 .lut_mask = "ff33";
defparam \SA[9]~reg0 .operation_mode = "normal";
defparam \SA[9]~reg0 .output_mode = "reg_only";
defparam \SA[9]~reg0 .register_cascade_mode = "off";
defparam \SA[9]~reg0 .sum_lutc_input = "datac";
defparam \SA[9]~reg0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y2_N6
maxii_lcell \Mux15~0 (
// Equation(s):
// \Mux15~0_combout  = (PS[2]) # ((PS[1] $ (PS[3])) # (!PS[0]))

	.clk(gnd),
	.dataa(PS[1]),
	.datab(PS[3]),
	.datac(PS[2]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux15~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux15~0 .lut_mask = "f6ff";
defparam \Mux15~0 .operation_mode = "normal";
defparam \Mux15~0 .output_mode = "comb_only";
defparam \Mux15~0 .register_cascade_mode = "off";
defparam \Mux15~0 .sum_lutc_input = "datac";
defparam \Mux15~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y3_N8
maxii_lcell \Mux15~1 (
// Equation(s):
// \Mux15~1_combout  = ((\IS.110~regout ) # ((!SetFWr[1] & Addr[20])))

	.clk(gnd),
	.dataa(vcc),
	.datab(SetFWr[1]),
	.datac(\IS.110~regout ),
	.datad(Addr[20]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux15~1_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux15~1 .lut_mask = "f3f0";
defparam \Mux15~1 .operation_mode = "normal";
defparam \Mux15~1 .output_mode = "comb_only";
defparam \Mux15~1 .register_cascade_mode = "off";
defparam \Mux15~1 .sum_lutc_input = "datac";
defparam \Mux15~1 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y3_N2
maxii_lcell \SA[10]~reg0 (
// Equation(s):
// \SA[10]~reg0_regout  = DFFEAS((\Mux15~0_combout ) # ((!PS[1] & ((\Mux15~1_combout ) # (!\RAMSpecSEL~1_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(PS[1]),
	.datab(\RAMSpecSEL~1_combout ),
	.datac(\Mux15~0_combout ),
	.datad(\Mux15~1_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SA[10]~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[10]~reg0 .lut_mask = "f5f1";
defparam \SA[10]~reg0 .operation_mode = "normal";
defparam \SA[10]~reg0 .output_mode = "reg_only";
defparam \SA[10]~reg0 .register_cascade_mode = "off";
defparam \SA[10]~reg0 .sum_lutc_input = "datac";
defparam \SA[10]~reg0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y4_N8
maxii_lcell \SA[11]~reg0 (
// Equation(s):
// \SA[11]~reg0_regout  = DFFEAS(((!SetFWr[1] & (Addr[21] & \SA~10_combout ))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(SetFWr[1]),
	.datac(Addr[21]),
	.datad(\SA~10_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SA[11]~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[11]~reg0 .lut_mask = "3000";
defparam \SA[11]~reg0 .operation_mode = "normal";
defparam \SA[11]~reg0 .output_mode = "reg_only";
defparam \SA[11]~reg0 .register_cascade_mode = "off";
defparam \SA[11]~reg0 .sum_lutc_input = "datac";
defparam \SA[11]~reg0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y3_N3
maxii_lcell \SA[12]~reg0 (
// Equation(s):
// \SA[12]~reg0_regout  = DFFEAS(((!SetFWr[1] & (Addr[22] & \SA~10_combout ))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(SetFWr[1]),
	.datac(Addr[22]),
	.datad(\SA~10_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SA[12]~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[12]~reg0 .lut_mask = "3000";
defparam \SA[12]~reg0 .operation_mode = "normal";
defparam \SA[12]~reg0 .output_mode = "reg_only";
defparam \SA[12]~reg0 .register_cascade_mode = "off";
defparam \SA[12]~reg0 .sum_lutc_input = "datac";
defparam \SA[12]~reg0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y1_N2
maxii_lcell \nRCS~3 (
// Equation(s):
// \nRCS~3_combout  = (\CXXXr~regout  & (\nWEr~regout  & ((\IOROMEN~regout ) # (!RAr[11]))))

	.clk(gnd),
	.dataa(\IOROMEN~regout ),
	.datab(RAr[11]),
	.datac(\CXXXr~regout ),
	.datad(\nWEr~regout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\nRCS~3_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \nRCS~3 .lut_mask = "b000";
defparam \nRCS~3 .operation_mode = "normal";
defparam \nRCS~3 .output_mode = "comb_only";
defparam \nRCS~3 .register_cascade_mode = "off";
defparam \nRCS~3 .sum_lutc_input = "datac";
defparam \nRCS~3 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y1_N9
maxii_lcell \nRCS~4 (
// Equation(s):
// \nRCS~4_combout  = ((!\Equal9~0  & ((\nRCS~3_combout ))))

	.clk(gnd),
	.dataa(vcc),
	.datab(\Equal9~0 ),
	.datac(vcc),
	.datad(\nRCS~3_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\nRCS~4_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \nRCS~4 .lut_mask = "3300";
defparam \nRCS~4 .operation_mode = "normal";
defparam \nRCS~4 .output_mode = "comb_only";
defparam \nRCS~4 .register_cascade_mode = "off";
defparam \nRCS~4 .sum_lutc_input = "datac";
defparam \nRCS~4 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y1_N9
maxii_lcell \Mux12~1 (
// Equation(s):
// \Mux12~1_combout  = (\nWEr~regout  & (((PS[1]))))

	.clk(gnd),
	.dataa(\nWEr~regout ),
	.datab(vcc),
	.datac(vcc),
	.datad(PS[1]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux12~1_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux12~1 .lut_mask = "aa00";
defparam \Mux12~1 .operation_mode = "normal";
defparam \Mux12~1 .output_mode = "comb_only";
defparam \Mux12~1 .register_cascade_mode = "off";
defparam \Mux12~1 .sum_lutc_input = "datac";
defparam \Mux12~1 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y1_N0
maxii_lcell \Mux12~2 (
// Equation(s):
// \Mux12~2_combout  = (\IS.111~regout  & (\Mux12~1_combout  & ((\RAMSpecSEL~1_combout ) # (\nRCS~4_combout ))))

	.clk(gnd),
	.dataa(\IS.111~regout ),
	.datab(\RAMSpecSEL~1_combout ),
	.datac(\nRCS~4_combout ),
	.datad(\Mux12~1_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux12~2_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux12~2 .lut_mask = "a800";
defparam \Mux12~2 .operation_mode = "normal";
defparam \Mux12~2 .output_mode = "comb_only";
defparam \Mux12~2 .register_cascade_mode = "off";
defparam \Mux12~2 .sum_lutc_input = "datac";
defparam \Mux12~2 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y1_N7
maxii_lcell \nRCS~5 (
// Equation(s):
// \nRCS~5_combout  = (\IS.110~regout ) # ((\IS.111~regout  & ((\nRCS~4_combout ) # (\RAMSpecSEL~1_combout ))))

	.clk(gnd),
	.dataa(\IS.111~regout ),
	.datab(\IS.110~regout ),
	.datac(\nRCS~4_combout ),
	.datad(\RAMSpecSEL~1_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\nRCS~5_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \nRCS~5 .lut_mask = "eeec";
defparam \nRCS~5 .operation_mode = "normal";
defparam \nRCS~5 .output_mode = "comb_only";
defparam \nRCS~5 .register_cascade_mode = "off";
defparam \nRCS~5 .sum_lutc_input = "datac";
defparam \nRCS~5 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y1_N6
maxii_lcell \Mux12~3 (
// Equation(s):
// \Mux12~3_combout  = (\Mux12~2_combout  & ((PS[1] $ (!PS[0])))) # (!\Mux12~2_combout  & (((PS[1]) # (!PS[0])) # (!\nRCS~5_combout )))

	.clk(gnd),
	.dataa(\Mux12~2_combout ),
	.datab(\nRCS~5_combout ),
	.datac(PS[1]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux12~3_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux12~3 .lut_mask = "f15f";
defparam \Mux12~3 .operation_mode = "normal";
defparam \Mux12~3 .output_mode = "comb_only";
defparam \Mux12~3 .register_cascade_mode = "off";
defparam \Mux12~3 .sum_lutc_input = "datac";
defparam \Mux12~3 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y1_N2
maxii_lcell \IS.000 (
// Equation(s):
// \IS.000~regout  = DFFEAS(VCC, GLOBAL(\C25M~combout ), VCC, , \IS~19_combout , , , , )

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\IS~19_combout ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\IS.000~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \IS.000 .lut_mask = "ffff";
defparam \IS.000 .operation_mode = "normal";
defparam \IS.000 .output_mode = "reg_only";
defparam \IS.000 .register_cascade_mode = "off";
defparam \IS.000 .sum_lutc_input = "datac";
defparam \IS.000 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y1_N3
maxii_lcell \nRCS~2 (
// Equation(s):
// \nRCS~2_combout  = (\IS.111~regout  & (LS[1] & (LS[0]))) # (!\IS.111~regout  & (((\IS.000~regout ))))

	.clk(gnd),
	.dataa(\IS.111~regout ),
	.datab(LS[1]),
	.datac(LS[0]),
	.datad(\IS.000~regout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\nRCS~2_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \nRCS~2 .lut_mask = "d580";
defparam \nRCS~2 .operation_mode = "normal";
defparam \nRCS~2 .output_mode = "comb_only";
defparam \nRCS~2 .register_cascade_mode = "off";
defparam \nRCS~2 .sum_lutc_input = "datac";
defparam \nRCS~2 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y1_N9
maxii_lcell \Mux12~0 (
// Equation(s):
// \Mux12~0_combout  = (PS[1] & (((PS[0] & !\nRCS~2_combout )))) # (!PS[1] & (((PS[0])) # (!\nRCS~1 )))

	.clk(gnd),
	.dataa(PS[1]),
	.datab(\nRCS~1 ),
	.datac(PS[0]),
	.datad(\nRCS~2_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux12~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux12~0 .lut_mask = "51f1";
defparam \Mux12~0 .operation_mode = "normal";
defparam \Mux12~0 .output_mode = "comb_only";
defparam \Mux12~0 .register_cascade_mode = "off";
defparam \Mux12~0 .sum_lutc_input = "datac";
defparam \Mux12~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y1_N4
maxii_lcell \nRCS~reg0 (
// Equation(s):
// \nRCS~reg0_regout  = DFFEAS((!PS[2] & ((PS[3] & ((!\Mux12~0_combout ))) # (!PS[3] & (!\Mux12~3_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(\Mux12~3_combout ),
	.datab(PS[3]),
	.datac(PS[2]),
	.datad(\Mux12~0_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\nRCS~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \nRCS~reg0 .lut_mask = "010d";
defparam \nRCS~reg0 .operation_mode = "normal";
defparam \nRCS~reg0 .output_mode = "reg_only";
defparam \nRCS~reg0 .register_cascade_mode = "off";
defparam \nRCS~reg0 .sum_lutc_input = "datac";
defparam \nRCS~reg0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y2_N2
maxii_lcell \nRAS~reg0 (
// Equation(s):
// \nRAS~reg0_regout  = DFFEAS((!PS[2] & ((PS[1] & (PS[3])) # (!PS[1] & (!PS[3] & PS[0])))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(PS[1]),
	.datab(PS[3]),
	.datac(PS[2]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\nRAS~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \nRAS~reg0 .lut_mask = "0908";
defparam \nRAS~reg0 .operation_mode = "normal";
defparam \nRAS~reg0 .output_mode = "reg_only";
defparam \nRAS~reg0 .register_cascade_mode = "off";
defparam \nRAS~reg0 .sum_lutc_input = "datac";
defparam \nRAS~reg0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y2_N3
maxii_lcell \nCAS~reg0 (
// Equation(s):
// \nCAS~reg0_regout  = DFFEAS((!PS[2] & ((PS[1] & (PS[3] $ (!PS[0]))) # (!PS[1] & (PS[3] & !PS[0])))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(PS[1]),
	.datab(PS[3]),
	.datac(PS[2]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\nCAS~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \nCAS~reg0 .lut_mask = "0806";
defparam \nCAS~reg0 .operation_mode = "normal";
defparam \nCAS~reg0 .output_mode = "reg_only";
defparam \nCAS~reg0 .register_cascade_mode = "off";
defparam \nCAS~reg0 .sum_lutc_input = "datac";
defparam \nCAS~reg0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y4_N4
maxii_lcell \Selector0~0 (
// Equation(s):
// \Selector0~0_combout  = (((!PS[1]) # (!\IS.001~regout )))

	.clk(gnd),
	.dataa(vcc),
	.datab(vcc),
	.datac(\IS.001~regout ),
	.datad(PS[1]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Selector0~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Selector0~0 .lut_mask = "0fff";
defparam \Selector0~0 .operation_mode = "normal";
defparam \Selector0~0 .output_mode = "comb_only";
defparam \Selector0~0 .register_cascade_mode = "off";
defparam \Selector0~0 .sum_lutc_input = "datac";
defparam \Selector0~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y4_N6
maxii_lcell \nSWE~reg0 (
// Equation(s):
// \nSWE~reg0_regout  = DFFEAS((PS[3] & (!PS[2] & ((!PS[0]) # (!\Selector0~0_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(\Selector0~0_combout ),
	.datab(PS[3]),
	.datac(PS[2]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\nSWE~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \nSWE~reg0 .lut_mask = "040c";
defparam \nSWE~reg0 .operation_mode = "normal";
defparam \nSWE~reg0 .output_mode = "reg_only";
defparam \nSWE~reg0 .register_cascade_mode = "off";
defparam \nSWE~reg0 .sum_lutc_input = "datac";
defparam \nSWE~reg0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y1_N1
maxii_lcell \Equal1~1 (
// Equation(s):
// \Equal1~1_combout  = (!PS[0] & (((!PS[2]))))

	.clk(gnd),
	.dataa(PS[0]),
	.datab(vcc),
	.datac(PS[2]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Equal1~1_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Equal1~1 .lut_mask = "0505";
defparam \Equal1~1 .operation_mode = "normal";
defparam \Equal1~1 .output_mode = "comb_only";
defparam \Equal1~1 .register_cascade_mode = "off";
defparam \Equal1~1 .sum_lutc_input = "datac";
defparam \Equal1~1 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y3_N1
maxii_lcell \Selector1~0 (
// Equation(s):
// \Selector1~0_combout  = (PS[3] & ((LS[0]) # ((PS[1])))) # (!PS[3] & (((RAr[0]) # (!PS[1]))))

	.clk(gnd),
	.dataa(PS[3]),
	.datab(LS[0]),
	.datac(RAr[0]),
	.datad(PS[1]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Selector1~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Selector1~0 .lut_mask = "fadd";
defparam \Selector1~0 .operation_mode = "normal";
defparam \Selector1~0 .output_mode = "comb_only";
defparam \Selector1~0 .register_cascade_mode = "off";
defparam \Selector1~0 .sum_lutc_input = "datac";
defparam \Selector1~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y3_N4
maxii_lcell \DQMH~0 (
// Equation(s):
// \DQMH~0_combout  = (PS[1] & (((!PS[3] & \RAMSpecSEL~1_combout )))) # (!PS[1] & (!\IS.110~regout  & (PS[3])))

	.clk(gnd),
	.dataa(PS[1]),
	.datab(\IS.110~regout ),
	.datac(PS[3]),
	.datad(\RAMSpecSEL~1_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\DQMH~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \DQMH~0 .lut_mask = "1a10";
defparam \DQMH~0 .operation_mode = "normal";
defparam \DQMH~0 .output_mode = "comb_only";
defparam \DQMH~0 .register_cascade_mode = "off";
defparam \DQMH~0 .sum_lutc_input = "datac";
defparam \DQMH~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y3_N9
maxii_lcell \DQML~reg0 (
// Equation(s):
// \DQML~reg0_regout  = DFFEAS((\Equal1~1_combout  & ((\DQMH~0_combout  & ((!Addr[0]))) # (!\DQMH~0_combout  & (!\Selector1~0_combout )))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(\Equal1~1_combout ),
	.datab(\Selector1~0_combout ),
	.datac(\DQMH~0_combout ),
	.datad(Addr[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\DQML~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \DQML~reg0 .lut_mask = "02a2";
defparam \DQML~reg0 .operation_mode = "normal";
defparam \DQML~reg0 .output_mode = "reg_only";
defparam \DQML~reg0 .register_cascade_mode = "off";
defparam \DQML~reg0 .sum_lutc_input = "datac";
defparam \DQML~reg0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y3_N0
maxii_lcell \Selector2~0 (
// Equation(s):
// \Selector2~0_combout  = (PS[3] & (((PS[1])) # (!LS[0]))) # (!PS[3] & (((!PS[1]) # (!RAr[0]))))

	.clk(gnd),
	.dataa(PS[3]),
	.datab(LS[0]),
	.datac(RAr[0]),
	.datad(PS[1]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Selector2~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Selector2~0 .lut_mask = "af77";
defparam \Selector2~0 .operation_mode = "normal";
defparam \Selector2~0 .output_mode = "comb_only";
defparam \Selector2~0 .register_cascade_mode = "off";
defparam \Selector2~0 .sum_lutc_input = "datac";
defparam \Selector2~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y3_N5
maxii_lcell \DQMH~reg0 (
// Equation(s):
// \DQMH~reg0_regout  = DFFEAS((\Equal1~1_combout  & ((\DQMH~0_combout  & (Addr[0])) # (!\DQMH~0_combout  & ((!\Selector2~0_combout ))))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(Addr[0]),
	.datab(\Selector2~0_combout ),
	.datac(\Equal1~1_combout ),
	.datad(\DQMH~0_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\DQMH~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \DQMH~reg0 .lut_mask = "a030";
defparam \DQMH~reg0 .operation_mode = "normal";
defparam \DQMH~reg0 .output_mode = "reg_only";
defparam \DQMH~reg0 .register_cascade_mode = "off";
defparam \DQMH~reg0 .sum_lutc_input = "datac";
defparam \DQMH~reg0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y1_N0
maxii_lcell \Mux11~0 (
// Equation(s):
// \Mux11~0_combout  = (PS[3] & (PS[1] & (\nRCS~2_combout ))) # (!PS[3] & (((\Mux12~2_combout ))))

	.clk(gnd),
	.dataa(PS[1]),
	.datab(\nRCS~2_combout ),
	.datac(PS[3]),
	.datad(\Mux12~2_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux11~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux11~0 .lut_mask = "8f80";
defparam \Mux11~0 .operation_mode = "normal";
defparam \Mux11~0 .output_mode = "comb_only";
defparam \Mux11~0 .register_cascade_mode = "off";
defparam \Mux11~0 .sum_lutc_input = "datac";
defparam \Mux11~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y1_N5
maxii_lcell \Mux11~1 (
// Equation(s):
// \Mux11~1_combout  = (\nRCS~5_combout  & ((PS[0]) # ((!PS[3] & \PS~0 ))))

	.clk(gnd),
	.dataa(PS[3]),
	.datab(\nRCS~5_combout ),
	.datac(\PS~0 ),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux11~1_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux11~1 .lut_mask = "cc40";
defparam \Mux11~1 .operation_mode = "normal";
defparam \Mux11~1 .output_mode = "comb_only";
defparam \Mux11~1 .register_cascade_mode = "off";
defparam \Mux11~1 .sum_lutc_input = "datac";
defparam \Mux11~1 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y1_N2
maxii_lcell \Mux11~2 (
// Equation(s):
// \Mux11~2_combout  = (\Mux11~1_combout ) # ((PS[3] & ((\nRCS~1 ) # (PS[0]))))

	.clk(gnd),
	.dataa(\Mux11~1_combout ),
	.datab(\nRCS~1 ),
	.datac(PS[3]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux11~2_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux11~2 .lut_mask = "faea";
defparam \Mux11~2 .operation_mode = "normal";
defparam \Mux11~2 .output_mode = "comb_only";
defparam \Mux11~2 .register_cascade_mode = "off";
defparam \Mux11~2 .sum_lutc_input = "datac";
defparam \Mux11~2 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y1_N3
maxii_lcell \Mux11~3 (
// Equation(s):
// \Mux11~3_combout  = (!PS[2] & ((\Mux11~0_combout ) # ((!PS[1] & \Mux11~2_combout ))))

	.clk(gnd),
	.dataa(PS[1]),
	.datab(\Mux11~0_combout ),
	.datac(PS[2]),
	.datad(\Mux11~2_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux11~3_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux11~3 .lut_mask = "0d0c";
defparam \Mux11~3 .operation_mode = "normal";
defparam \Mux11~3 .output_mode = "comb_only";
defparam \Mux11~3 .register_cascade_mode = "off";
defparam \Mux11~3 .sum_lutc_input = "datac";
defparam \Mux11~3 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y1_N7
maxii_lcell \Equal2~0 (
// Equation(s):
// \Equal2~0_combout  = (PS[1] & (((PS[2] & PS[0]))))

	.clk(gnd),
	.dataa(PS[1]),
	.datab(vcc),
	.datac(PS[2]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Equal2~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Equal2~0 .lut_mask = "a000";
defparam \Equal2~0 .operation_mode = "normal";
defparam \Equal2~0 .output_mode = "comb_only";
defparam \Equal2~0 .register_cascade_mode = "off";
defparam \Equal2~0 .sum_lutc_input = "datac";
defparam \Equal2~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y1_N8
maxii_lcell \RCKE~reg0 (
// Equation(s):
// \RCKE~reg0_regout  = DFFEAS((!\Mux11~3_combout  & (((PS[3]) # (!\Equal2~0_combout )) # (!\nRCS~1 ))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(\Mux11~3_combout ),
	.datab(\nRCS~1 ),
	.datac(PS[3]),
	.datad(\Equal2~0_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\RCKE~reg0_regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RCKE~reg0 .lut_mask = "5155";
defparam \RCKE~reg0 .operation_mode = "normal";
defparam \RCKE~reg0 .output_mode = "reg_only";
defparam \RCKE~reg0 .register_cascade_mode = "off";
defparam \RCKE~reg0 .sum_lutc_input = "datac";
defparam \RCKE~reg0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y2_N1
maxii_lcell \IS.101 (
// Equation(s):
// \IS.101~regout  = DFFEAS((!LS[2] & (\Equal5~0_combout  & (!LS[0] & !LS[13]))), GLOBAL(\C25M~combout ), VCC, , \IS~19_combout , , , , )

	.clk(\C25M~combout ),
	.dataa(LS[2]),
	.datab(\Equal5~0_combout ),
	.datac(LS[0]),
	.datad(LS[13]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\IS~19_combout ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\IS.101~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \IS.101 .lut_mask = "0004";
defparam \IS.101 .operation_mode = "normal";
defparam \IS.101 .output_mode = "reg_only";
defparam \IS.101 .register_cascade_mode = "off";
defparam \IS.101 .sum_lutc_input = "datac";
defparam \IS.101 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y4_N9
maxii_lcell FCS(
// Equation(s):
// \FCS~regout  = DFFEAS((\IS.110~regout ) # ((\IS.100~regout ) # ((\IS.101~regout ))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(\IS.110~regout ),
	.datab(\IS.100~regout ),
	.datac(\IS.101~regout ),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\FCS~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam FCS.lut_mask = "fefe";
defparam FCS.operation_mode = "normal";
defparam FCS.output_mode = "reg_only";
defparam FCS.register_cascade_mode = "off";
defparam FCS.sum_lutc_input = "datac";
defparam FCS.synch_mode = "off";
// synopsys translate_on

// Location: LC_X3_Y1_N1
maxii_lcell FCKOE(
// Equation(s):
// \FCKOE~regout  = DFFEAS((((\IS.111~regout ) # (\IS.000~regout ))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\IS.111~regout ),
	.datad(\IS.000~regout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\FCKOE~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam FCKOE.lut_mask = "fff0";
defparam FCKOE.operation_mode = "normal";
defparam FCKOE.output_mode = "reg_only";
defparam FCKOE.register_cascade_mode = "off";
defparam FCKOE.sum_lutc_input = "datac";
defparam FCKOE.synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y4_N2
maxii_lcell FCKout(
// Equation(s):
// \FCKout~regout  = DFFEAS(((!\IS.101~regout  & ((PS[3]) # (!\IS.110~regout )))) # (!PS[0]), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(\IS.110~regout ),
	.datab(PS[3]),
	.datac(\IS.101~regout ),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\FCKout~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam FCKout.lut_mask = "0dff";
defparam FCKout.operation_mode = "normal";
defparam FCKout.output_mode = "reg_only";
defparam FCKout.register_cascade_mode = "off";
defparam FCKout.sum_lutc_input = "datac";
defparam FCKout.synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y4_N7
maxii_lcell \RDD[1]~23 (
// Equation(s):
// \RDD[1]~23_combout  = (!RAr[3] & (\always9~0_combout  & (!RAr[2] & !RAr[1])))

	.clk(gnd),
	.dataa(RAr[3]),
	.datab(\always9~0_combout ),
	.datac(RAr[2]),
	.datad(RAr[1]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\RDD[1]~23_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RDD[1]~23 .lut_mask = "0004";
defparam \RDD[1]~23 .operation_mode = "normal";
defparam \RDD[1]~23 .output_mode = "comb_only";
defparam \RDD[1]~23 .register_cascade_mode = "off";
defparam \RDD[1]~23 .sum_lutc_input = "datac";
defparam \RDD[1]~23 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X4_Y3_N1
maxii_lcell \RDD[1]~22 (
// Equation(s):
// \RDD[1]~22_combout  = (!RAr[3] & (!RAr[2] & (!RAr[0] & \always9~0_combout )))

	.clk(gnd),
	.dataa(RAr[3]),
	.datab(RAr[2]),
	.datac(RAr[0]),
	.datad(\always9~0_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\RDD[1]~22_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RDD[1]~22 .lut_mask = "0100";
defparam \RDD[1]~22 .operation_mode = "normal";
defparam \RDD[1]~22 .output_mode = "comb_only";
defparam \RDD[1]~22 .register_cascade_mode = "off";
defparam \RDD[1]~22 .sum_lutc_input = "datac";
defparam \RDD[1]~22 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y3_N7
maxii_lcell \RDD~4 (
// Equation(s):
// \RDD~4_combout  = (\RDD[1]~23_combout  & ((Addr[8]) # ((\RDD[1]~22_combout )))) # (!\RDD[1]~23_combout  & (((!\RDD[1]~22_combout  & \SD[0]~0 ))))

	.clk(gnd),
	.dataa(\RDD[1]~23_combout ),
	.datab(Addr[8]),
	.datac(\RDD[1]~22_combout ),
	.datad(\SD[0]~0 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\RDD~4_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RDD~4 .lut_mask = "ada8";
defparam \RDD~4 .operation_mode = "normal";
defparam \RDD~4 .output_mode = "comb_only";
defparam \RDD~4 .register_cascade_mode = "off";
defparam \RDD~4 .sum_lutc_input = "datac";
defparam \RDD~4 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y4_N5
maxii_lcell \Equal20~0 (
// Equation(s):
// \Equal20~0_combout  = (!PS[1] & (!PS[3] & (PS[2] & PS[0])))

	.clk(gnd),
	.dataa(PS[1]),
	.datab(PS[3]),
	.datac(PS[2]),
	.datad(PS[0]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Equal20~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Equal20~0 .lut_mask = "1000";
defparam \Equal20~0 .operation_mode = "normal";
defparam \Equal20~0 .output_mode = "comb_only";
defparam \Equal20~0 .register_cascade_mode = "off";
defparam \Equal20~0 .sum_lutc_input = "datac";
defparam \Equal20~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y3_N4
maxii_lcell \RDD[0] (
// Equation(s):
// RDD[0] = DFFEAS((\RDD~4_combout  & ((Addr[0]) # ((!\RDD[1]~22_combout )))) # (!\RDD~4_combout  & (((\RDD[1]~22_combout  & Addr[16])))), !GLOBAL(\C25M~combout ), VCC, , \Equal20~0_combout , , , , )

	.clk(!\C25M~combout ),
	.dataa(Addr[0]),
	.datab(\RDD~4_combout ),
	.datac(\RDD[1]~22_combout ),
	.datad(Addr[16]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal20~0_combout ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(RDD[0]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RDD[0] .lut_mask = "bc8c";
defparam \RDD[0] .operation_mode = "normal";
defparam \RDD[0] .output_mode = "reg_only";
defparam \RDD[0] .register_cascade_mode = "off";
defparam \RDD[0] .sum_lutc_input = "datac";
defparam \RDD[0] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y3_N1
maxii_lcell \RDD~6 (
// Equation(s):
// \RDD~6_combout  = (\RDD[1]~23_combout  & ((Addr[9]) # ((\RDD[1]~22_combout )))) # (!\RDD[1]~23_combout  & (((!\RDD[1]~22_combout  & \SD[1]~1 ))))

	.clk(gnd),
	.dataa(\RDD[1]~23_combout ),
	.datab(Addr[9]),
	.datac(\RDD[1]~22_combout ),
	.datad(\SD[1]~1 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\RDD~6_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RDD~6 .lut_mask = "ada8";
defparam \RDD~6 .operation_mode = "normal";
defparam \RDD~6 .output_mode = "comb_only";
defparam \RDD~6 .register_cascade_mode = "off";
defparam \RDD~6 .sum_lutc_input = "datac";
defparam \RDD~6 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y3_N2
maxii_lcell \RDD[1] (
// Equation(s):
// RDD[1] = DFFEAS((\RDD[1]~22_combout  & ((\RDD~6_combout  & ((Addr[1]))) # (!\RDD~6_combout  & (Addr[17])))) # (!\RDD[1]~22_combout  & (\RDD~6_combout )), !GLOBAL(\C25M~combout ), VCC, , \Equal20~0_combout , , , , )

	.clk(!\C25M~combout ),
	.dataa(\RDD[1]~22_combout ),
	.datab(\RDD~6_combout ),
	.datac(Addr[17]),
	.datad(Addr[1]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal20~0_combout ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(RDD[1]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RDD[1] .lut_mask = "ec64";
defparam \RDD[1] .operation_mode = "normal";
defparam \RDD[1] .output_mode = "reg_only";
defparam \RDD[1] .register_cascade_mode = "off";
defparam \RDD[1] .sum_lutc_input = "datac";
defparam \RDD[1] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y3_N9
maxii_lcell \RDD~8 (
// Equation(s):
// \RDD~8_combout  = (\RDD[1]~23_combout  & (((\RDD[1]~22_combout ) # (Addr[10])))) # (!\RDD[1]~23_combout  & (\SD[2]~2  & (!\RDD[1]~22_combout )))

	.clk(gnd),
	.dataa(\RDD[1]~23_combout ),
	.datab(\SD[2]~2 ),
	.datac(\RDD[1]~22_combout ),
	.datad(Addr[10]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\RDD~8_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RDD~8 .lut_mask = "aea4";
defparam \RDD~8 .operation_mode = "normal";
defparam \RDD~8 .output_mode = "comb_only";
defparam \RDD~8 .register_cascade_mode = "off";
defparam \RDD~8 .sum_lutc_input = "datac";
defparam \RDD~8 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y3_N0
maxii_lcell \RDD[2] (
// Equation(s):
// RDD[2] = DFFEAS((\RDD[1]~22_combout  & ((\RDD~8_combout  & (Addr[2])) # (!\RDD~8_combout  & ((Addr[18]))))) # (!\RDD[1]~22_combout  & (\RDD~8_combout )), !GLOBAL(\C25M~combout ), VCC, , \Equal20~0_combout , , , , )

	.clk(!\C25M~combout ),
	.dataa(\RDD[1]~22_combout ),
	.datab(\RDD~8_combout ),
	.datac(Addr[2]),
	.datad(Addr[18]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal20~0_combout ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(RDD[2]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RDD[2] .lut_mask = "e6c4";
defparam \RDD[2] .operation_mode = "normal";
defparam \RDD[2] .output_mode = "reg_only";
defparam \RDD[2] .register_cascade_mode = "off";
defparam \RDD[2] .sum_lutc_input = "datac";
defparam \RDD[2] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y3_N8
maxii_lcell \RDD~10 (
// Equation(s):
// \RDD~10_combout  = (\RDD[1]~22_combout  & (((\RDD[1]~23_combout )))) # (!\RDD[1]~22_combout  & ((\RDD[1]~23_combout  & (Addr[11])) # (!\RDD[1]~23_combout  & ((\SD[3]~3 )))))

	.clk(gnd),
	.dataa(\RDD[1]~22_combout ),
	.datab(Addr[11]),
	.datac(\RDD[1]~23_combout ),
	.datad(\SD[3]~3 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\RDD~10_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RDD~10 .lut_mask = "e5e0";
defparam \RDD~10 .operation_mode = "normal";
defparam \RDD~10 .output_mode = "comb_only";
defparam \RDD~10 .register_cascade_mode = "off";
defparam \RDD~10 .sum_lutc_input = "datac";
defparam \RDD~10 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y3_N5
maxii_lcell \RDD[3] (
// Equation(s):
// RDD[3] = DFFEAS((\RDD[1]~22_combout  & ((\RDD~10_combout  & (Addr[3])) # (!\RDD~10_combout  & ((Addr[19]))))) # (!\RDD[1]~22_combout  & (((\RDD~10_combout )))), !GLOBAL(\C25M~combout ), VCC, , \Equal20~0_combout , , , , )

	.clk(!\C25M~combout ),
	.dataa(Addr[3]),
	.datab(Addr[19]),
	.datac(\RDD[1]~22_combout ),
	.datad(\RDD~10_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal20~0_combout ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(RDD[3]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RDD[3] .lut_mask = "afc0";
defparam \RDD[3] .operation_mode = "normal";
defparam \RDD[3] .output_mode = "reg_only";
defparam \RDD[3] .register_cascade_mode = "off";
defparam \RDD[3] .sum_lutc_input = "datac";
defparam \RDD[3] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y4_N4
maxii_lcell \RDD[4]~12 (
// Equation(s):
// \RDD[4]~12_combout  = ((RAr[0] $ (!RAr[1])) # (!\always9~0_combout )) # (!\RAMRegSpecSEL~1 )

	.clk(gnd),
	.dataa(\RAMRegSpecSEL~1 ),
	.datab(\always9~0_combout ),
	.datac(RAr[0]),
	.datad(RAr[1]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\RDD[4]~12_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RDD[4]~12 .lut_mask = "f77f";
defparam \RDD[4]~12 .operation_mode = "normal";
defparam \RDD[4]~12 .output_mode = "comb_only";
defparam \RDD[4]~12 .register_cascade_mode = "off";
defparam \RDD[4]~12 .sum_lutc_input = "datac";
defparam \RDD[4]~12 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y4_N8
maxii_lcell \RDD~14 (
// Equation(s):
// \RDD~14_combout  = (\RDD[4]~12_combout  & (((Addr[4] & \RDD[1]~23_combout )))) # (!\RDD[4]~12_combout  & ((Addr[12]) # ((!\RDD[1]~23_combout ))))

	.clk(gnd),
	.dataa(\RDD[4]~12_combout ),
	.datab(Addr[12]),
	.datac(Addr[4]),
	.datad(\RDD[1]~23_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\RDD~14_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RDD~14 .lut_mask = "e455";
defparam \RDD~14 .operation_mode = "normal";
defparam \RDD~14 .output_mode = "comb_only";
defparam \RDD~14 .register_cascade_mode = "off";
defparam \RDD~14 .sum_lutc_input = "datac";
defparam \RDD~14 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y4_N9
maxii_lcell \RDD[4]~13 (
// Equation(s):
// \RDD[4]~13_combout  = (!\RDD[1]~23_combout  & ((\RDD[4]~12_combout ) # ((!SetFWr[1]))))

	.clk(gnd),
	.dataa(\RDD[4]~12_combout ),
	.datab(\RDD[1]~23_combout ),
	.datac(SetFWr[1]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\RDD[4]~13_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RDD[4]~13 .lut_mask = "2323";
defparam \RDD[4]~13 .operation_mode = "normal";
defparam \RDD[4]~13 .output_mode = "comb_only";
defparam \RDD[4]~13 .register_cascade_mode = "off";
defparam \RDD[4]~13 .sum_lutc_input = "datac";
defparam \RDD[4]~13 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y4_N5
maxii_lcell \RDD[4] (
// Equation(s):
// RDD[4] = DFFEAS((\RDD~14_combout  & (((Addr[20])) # (!\RDD[4]~13_combout ))) # (!\RDD~14_combout  & (\RDD[4]~13_combout  & (\SD[4]~4 ))), !GLOBAL(\C25M~combout ), VCC, , \Equal20~0_combout , , , , )

	.clk(!\C25M~combout ),
	.dataa(\RDD~14_combout ),
	.datab(\RDD[4]~13_combout ),
	.datac(\SD[4]~4 ),
	.datad(Addr[20]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal20~0_combout ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(RDD[4]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RDD[4] .lut_mask = "ea62";
defparam \RDD[4] .operation_mode = "normal";
defparam \RDD[4] .output_mode = "reg_only";
defparam \RDD[4] .register_cascade_mode = "off";
defparam \RDD[4] .sum_lutc_input = "datac";
defparam \RDD[4] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y4_N0
maxii_lcell \RDD~16 (
// Equation(s):
// \RDD~16_combout  = (\RDD[4]~12_combout  & (\RDD[1]~23_combout  & ((Addr[5])))) # (!\RDD[4]~12_combout  & (((Addr[13])) # (!\RDD[1]~23_combout )))

	.clk(gnd),
	.dataa(\RDD[4]~12_combout ),
	.datab(\RDD[1]~23_combout ),
	.datac(Addr[13]),
	.datad(Addr[5]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\RDD~16_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RDD~16 .lut_mask = "d951";
defparam \RDD~16 .operation_mode = "normal";
defparam \RDD~16 .output_mode = "comb_only";
defparam \RDD~16 .register_cascade_mode = "off";
defparam \RDD~16 .sum_lutc_input = "datac";
defparam \RDD~16 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y4_N1
maxii_lcell \RDD[5] (
// Equation(s):
// RDD[5] = DFFEAS((\RDD[4]~13_combout  & ((\RDD~16_combout  & ((Addr[21]))) # (!\RDD~16_combout  & (\SD[5]~5 )))) # (!\RDD[4]~13_combout  & (((\RDD~16_combout )))), !GLOBAL(\C25M~combout ), VCC, , \Equal20~0_combout , , , , )

	.clk(!\C25M~combout ),
	.dataa(\SD[5]~5 ),
	.datab(\RDD[4]~13_combout ),
	.datac(Addr[21]),
	.datad(\RDD~16_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal20~0_combout ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(RDD[5]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RDD[5] .lut_mask = "f388";
defparam \RDD[5] .operation_mode = "normal";
defparam \RDD[5] .output_mode = "reg_only";
defparam \RDD[5] .register_cascade_mode = "off";
defparam \RDD[5] .sum_lutc_input = "datac";
defparam \RDD[5] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y4_N6
maxii_lcell \RDD~18 (
// Equation(s):
// \RDD~18_combout  = (\RDD[1]~23_combout  & ((\RDD[4]~12_combout  & ((Addr[6]))) # (!\RDD[4]~12_combout  & (Addr[14])))) # (!\RDD[1]~23_combout  & (((!\RDD[4]~12_combout ))))

	.clk(gnd),
	.dataa(Addr[14]),
	.datab(\RDD[1]~23_combout ),
	.datac(\RDD[4]~12_combout ),
	.datad(Addr[6]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\RDD~18_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RDD~18 .lut_mask = "cb0b";
defparam \RDD~18 .operation_mode = "normal";
defparam \RDD~18 .output_mode = "comb_only";
defparam \RDD~18 .register_cascade_mode = "off";
defparam \RDD~18 .sum_lutc_input = "datac";
defparam \RDD~18 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y4_N2
maxii_lcell \RDD[6] (
// Equation(s):
// RDD[6] = DFFEAS((\RDD[4]~13_combout  & ((\RDD~18_combout  & (Addr[22])) # (!\RDD~18_combout  & ((\SD[6]~6 ))))) # (!\RDD[4]~13_combout  & (((\RDD~18_combout )))), !GLOBAL(\C25M~combout ), VCC, , \Equal20~0_combout , , , , )

	.clk(!\C25M~combout ),
	.dataa(Addr[22]),
	.datab(\RDD[4]~13_combout ),
	.datac(\RDD~18_combout ),
	.datad(\SD[6]~6 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal20~0_combout ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(RDD[6]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RDD[6] .lut_mask = "bcb0";
defparam \RDD[6] .operation_mode = "normal";
defparam \RDD[6] .output_mode = "reg_only";
defparam \RDD[6] .register_cascade_mode = "off";
defparam \RDD[6] .sum_lutc_input = "datac";
defparam \RDD[6] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X6_Y4_N0
maxii_lcell \RDD~20 (
// Equation(s):
// \RDD~20_combout  = (\RDD[4]~12_combout  & (Addr[7] & ((\RDD[1]~23_combout )))) # (!\RDD[4]~12_combout  & (((Addr[15]) # (!\RDD[1]~23_combout ))))

	.clk(gnd),
	.dataa(Addr[7]),
	.datab(\RDD[4]~12_combout ),
	.datac(Addr[15]),
	.datad(\RDD[1]~23_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\RDD~20_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RDD~20 .lut_mask = "b833";
defparam \RDD~20 .operation_mode = "normal";
defparam \RDD~20 .output_mode = "comb_only";
defparam \RDD~20 .register_cascade_mode = "off";
defparam \RDD~20 .sum_lutc_input = "datac";
defparam \RDD~20 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X5_Y4_N3
maxii_lcell \RDD[7] (
// Equation(s):
// RDD[7] = DFFEAS((\RDD~20_combout  & (((Addr[23]) # (!\RDD[4]~13_combout )))) # (!\RDD~20_combout  & (\SD[7]~7  & ((\RDD[4]~13_combout )))), !GLOBAL(\C25M~combout ), VCC, , \Equal20~0_combout , , , , )

	.clk(!\C25M~combout ),
	.dataa(\RDD~20_combout ),
	.datab(\SD[7]~7 ),
	.datac(Addr[23]),
	.datad(\RDD[4]~13_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\Equal20~0_combout ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(RDD[7]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \RDD[7] .lut_mask = "e4aa";
defparam \RDD[7] .operation_mode = "normal";
defparam \RDD[7] .output_mode = "reg_only";
defparam \RDD[7] .register_cascade_mode = "off";
defparam \RDD[7] .sum_lutc_input = "datac";
defparam \RDD[7] .synch_mode = "off";
// synopsys translate_on

// Location: LC_X7_Y1_N6
maxii_lcell \WRD[0] (
// Equation(s):
// WRD[0] = DFFEAS((\IS.110~regout  & (\MOSI~0 )) # (!\IS.110~regout  & (((\RD[0]~0 )))), GLOBAL(\C25M~combout ), VCC, , , WRD[0], , , PS[0])

	.clk(\C25M~combout ),
	.dataa(\IS.110~regout ),
	.datab(\MOSI~0 ),
	.datac(WRD[0]),
	.datad(\RD[0]~0 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(PS[0]),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(WRD[0]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \WRD[0] .lut_mask = "dd88";
defparam \WRD[0] .operation_mode = "normal";
defparam \WRD[0] .output_mode = "reg_only";
defparam \WRD[0] .register_cascade_mode = "off";
defparam \WRD[0] .sum_lutc_input = "datac";
defparam \WRD[0] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X5_Y1_N4
maxii_lcell SDOE(
// Equation(s):
// \SDOE~regout  = DFFEAS((((\Equal19~0_combout  & \nRCS~1 ))), GLOBAL(\C25M~combout ), VCC, , , , , , )

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\Equal19~0_combout ),
	.datad(\nRCS~1 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SDOE~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam SDOE.lut_mask = "f000";
defparam SDOE.operation_mode = "normal";
defparam SDOE.output_mode = "reg_only";
defparam SDOE.register_cascade_mode = "off";
defparam SDOE.sum_lutc_input = "datac";
defparam SDOE.synch_mode = "off";
// synopsys translate_on

// Location: PIN_16,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
maxii_io \MISO~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\MISO~combout ),
	.padio(MISO));
// synopsys translate_off
defparam \MISO~I .bus_hold = "true";
defparam \MISO~I .operation_mode = "input";
// synopsys translate_on

// Location: LC_X7_Y1_N7
maxii_lcell \WRD[1] (
// Equation(s):
// WRD[1] = DFFEAS((\IS.110~regout  & (\MISO~combout )) # (!\IS.110~regout  & (((\RD[1]~1 )))), GLOBAL(\C25M~combout ), VCC, , , WRD[1], , , PS[0])

	.clk(\C25M~combout ),
	.dataa(\IS.110~regout ),
	.datab(\MISO~combout ),
	.datac(WRD[1]),
	.datad(\RD[1]~1 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(PS[0]),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(WRD[1]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \WRD[1] .lut_mask = "dd88";
defparam \WRD[1] .operation_mode = "normal";
defparam \WRD[1] .output_mode = "reg_only";
defparam \WRD[1] .register_cascade_mode = "off";
defparam \WRD[1] .sum_lutc_input = "datac";
defparam \WRD[1] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X7_Y1_N2
maxii_lcell \WRD[2] (
// Equation(s):
// WRD[2] = DFFEAS(((\IS.110~regout  & (WRD[0])) # (!\IS.110~regout  & ((\RD[2]~2 )))), GLOBAL(\C25M~combout ), VCC, , , WRD[2], , , PS[0])

	.clk(\C25M~combout ),
	.dataa(WRD[0]),
	.datab(\RD[2]~2 ),
	.datac(WRD[2]),
	.datad(\IS.110~regout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(PS[0]),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(WRD[2]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \WRD[2] .lut_mask = "aacc";
defparam \WRD[2] .operation_mode = "normal";
defparam \WRD[2] .output_mode = "reg_only";
defparam \WRD[2] .register_cascade_mode = "off";
defparam \WRD[2] .sum_lutc_input = "datac";
defparam \WRD[2] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X7_Y1_N3
maxii_lcell \WRD[3] (
// Equation(s):
// WRD[3] = DFFEAS(((\IS.110~regout  & (WRD[1])) # (!\IS.110~regout  & ((\RD[3]~3 )))), GLOBAL(\C25M~combout ), VCC, , , WRD[3], , , PS[0])

	.clk(\C25M~combout ),
	.dataa(WRD[1]),
	.datab(\RD[3]~3 ),
	.datac(WRD[3]),
	.datad(\IS.110~regout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(PS[0]),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(WRD[3]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \WRD[3] .lut_mask = "aacc";
defparam \WRD[3] .operation_mode = "normal";
defparam \WRD[3] .output_mode = "reg_only";
defparam \WRD[3] .register_cascade_mode = "off";
defparam \WRD[3] .sum_lutc_input = "datac";
defparam \WRD[3] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X7_Y1_N5
maxii_lcell \WRD[4] (
// Equation(s):
// WRD[4] = DFFEAS((\IS.110~regout  & (((WRD[2])))) # (!\IS.110~regout  & (\RD[4]~4 )), GLOBAL(\C25M~combout ), VCC, , , WRD[4], , , PS[0])

	.clk(\C25M~combout ),
	.dataa(\IS.110~regout ),
	.datab(\RD[4]~4 ),
	.datac(WRD[4]),
	.datad(WRD[2]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(PS[0]),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(WRD[4]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \WRD[4] .lut_mask = "ee44";
defparam \WRD[4] .operation_mode = "normal";
defparam \WRD[4] .output_mode = "reg_only";
defparam \WRD[4] .register_cascade_mode = "off";
defparam \WRD[4] .sum_lutc_input = "datac";
defparam \WRD[4] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X7_Y1_N8
maxii_lcell \WRD[5] (
// Equation(s):
// WRD[5] = DFFEAS((\IS.110~regout  & (((WRD[3])))) # (!\IS.110~regout  & (\RD[5]~5 )), GLOBAL(\C25M~combout ), VCC, , , WRD[5], , , PS[0])

	.clk(\C25M~combout ),
	.dataa(\IS.110~regout ),
	.datab(\RD[5]~5 ),
	.datac(WRD[5]),
	.datad(WRD[3]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(PS[0]),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(WRD[5]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \WRD[5] .lut_mask = "ee44";
defparam \WRD[5] .operation_mode = "normal";
defparam \WRD[5] .output_mode = "reg_only";
defparam \WRD[5] .register_cascade_mode = "off";
defparam \WRD[5] .sum_lutc_input = "datac";
defparam \WRD[5] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X7_Y1_N9
maxii_lcell \WRD[6] (
// Equation(s):
// WRD[6] = DFFEAS(((\IS.110~regout  & (WRD[4])) # (!\IS.110~regout  & ((\RD[6]~6 )))), GLOBAL(\C25M~combout ), VCC, , , WRD[6], , , PS[0])

	.clk(\C25M~combout ),
	.dataa(WRD[4]),
	.datab(\RD[6]~6 ),
	.datac(WRD[6]),
	.datad(\IS.110~regout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(PS[0]),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(WRD[6]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \WRD[6] .lut_mask = "aacc";
defparam \WRD[6] .operation_mode = "normal";
defparam \WRD[6] .output_mode = "reg_only";
defparam \WRD[6] .register_cascade_mode = "off";
defparam \WRD[6] .sum_lutc_input = "datac";
defparam \WRD[6] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X7_Y1_N4
maxii_lcell \WRD[7] (
// Equation(s):
// WRD[7] = DFFEAS((\IS.110~regout  & (((WRD[5])))) # (!\IS.110~regout  & (\RD[7]~7 )), GLOBAL(\C25M~combout ), VCC, , , WRD[7], , , PS[0])

	.clk(\C25M~combout ),
	.dataa(\IS.110~regout ),
	.datab(\RD[7]~7 ),
	.datac(WRD[7]),
	.datad(WRD[5]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(PS[0]),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(WRD[7]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \WRD[7] .lut_mask = "ee44";
defparam \WRD[7] .operation_mode = "normal";
defparam \WRD[7] .output_mode = "reg_only";
defparam \WRD[7] .register_cascade_mode = "off";
defparam \WRD[7] .sum_lutc_input = "datac";
defparam \WRD[7] .synch_mode = "on";
// synopsys translate_on

// Location: LC_X4_Y2_N2
maxii_lcell \Mux2~0 (
// Equation(s):
// \Mux2~0_combout  = (LS[1] & (!PS[1] & ((!LS[2])))) # (!LS[1] & (PS[1] & (!SetFWr[1] & LS[2])))

	.clk(gnd),
	.dataa(LS[1]),
	.datab(PS[1]),
	.datac(SetFWr[1]),
	.datad(LS[2]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux2~0_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux2~0 .lut_mask = "0422";
defparam \Mux2~0 .operation_mode = "normal";
defparam \Mux2~0 .output_mode = "comb_only";
defparam \Mux2~0 .register_cascade_mode = "off";
defparam \Mux2~0 .sum_lutc_input = "datac";
defparam \Mux2~0 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y1_N8
maxii_lcell \Mux2~1 (
// Equation(s):
// \Mux2~1_combout  = (((LS[0] & \Mux2~0_combout )))

	.clk(gnd),
	.dataa(vcc),
	.datab(vcc),
	.datac(LS[0]),
	.datad(\Mux2~0_combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux2~1_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux2~1 .lut_mask = "f000";
defparam \Mux2~1 .operation_mode = "normal";
defparam \Mux2~1 .output_mode = "comb_only";
defparam \Mux2~1 .register_cascade_mode = "off";
defparam \Mux2~1 .sum_lutc_input = "datac";
defparam \Mux2~1 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y1_N9
maxii_lcell \Mux2~3 (
// Equation(s):
// \Mux2~3_combout  = (((LS[0] & \Mux2~2 )))

	.clk(gnd),
	.dataa(vcc),
	.datab(vcc),
	.datac(LS[0]),
	.datad(\Mux2~2 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Mux2~3_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Mux2~3 .lut_mask = "f000";
defparam \Mux2~3 .operation_mode = "normal";
defparam \Mux2~3 .output_mode = "comb_only";
defparam \Mux2~3 .register_cascade_mode = "off";
defparam \Mux2~3 .sum_lutc_input = "datac";
defparam \Mux2~3 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y1_N6
maxii_lcell \SA[1]~14 (
// Equation(s):
// \SA[1]~14_combout  = PS[3] $ ((((PS[1]))))

	.clk(gnd),
	.dataa(PS[3]),
	.datab(vcc),
	.datac(PS[1]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\SA[1]~14_combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \SA[1]~14 .lut_mask = "5a5a";
defparam \SA[1]~14 .operation_mode = "normal";
defparam \SA[1]~14 .output_mode = "comb_only";
defparam \SA[1]~14 .register_cascade_mode = "off";
defparam \SA[1]~14 .sum_lutc_input = "datac";
defparam \SA[1]~14 .synch_mode = "off";
// synopsys translate_on

// Location: LC_X2_Y1_N4
maxii_lcell MOSIout(
// Equation(s):
// \MOSIout~regout  = DFFEAS((PS[2] & (((\Mux2~3_combout )))) # (!PS[2] & (\Mux2~1_combout  & ((\SA[1]~14_combout )))), GLOBAL(\C25M~combout ), VCC, , PS[0], , , !PS[0], )

	.clk(\C25M~combout ),
	.dataa(\Mux2~1_combout ),
	.datab(\Mux2~3_combout ),
	.datac(\SA[1]~14_combout ),
	.datad(PS[2]),
	.aclr(gnd),
	.aload(gnd),
	.sclr(!PS[0]),
	.sload(gnd),
	.ena(PS[0]),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\MOSIout~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam MOSIout.lut_mask = "cca0";
defparam MOSIout.operation_mode = "normal";
defparam MOSIout.output_mode = "reg_only";
defparam MOSIout.register_cascade_mode = "off";
defparam MOSIout.sum_lutc_input = "datac";
defparam MOSIout.synch_mode = "on";
// synopsys translate_on

// Location: LC_X2_Y2_N8
maxii_lcell MOSIOE(
// Equation(s):
// \MOSIOE~regout  = DFFEAS(GND, GLOBAL(\C25M~combout ), VCC, , , \IS.101~regout , , , VCC)

	.clk(\C25M~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\IS.101~regout ),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\MOSIOE~regout ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam MOSIOE.lut_mask = "0000";
defparam MOSIOE.operation_mode = "normal";
defparam MOSIOE.output_mode = "reg_only";
defparam MOSIOE.register_cascade_mode = "off";
defparam MOSIOE.sum_lutc_input = "datac";
defparam MOSIOE.synch_mode = "on";
// synopsys translate_on

// Location: PIN_30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \nRESout~I (
	.datain(\nRESout~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(nRESout));
// synopsys translate_off
defparam \nRESout~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_20,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
maxii_io \INTout~I (
	.datain(\INTin~combout ),
	.oe(vcc),
	.combout(),
	.padio(INTout));
// synopsys translate_off
defparam \INTout~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_18,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
maxii_io \DMAout~I (
	.datain(\DMAin~combout ),
	.oe(vcc),
	.combout(),
	.padio(DMAout));
// synopsys translate_off
defparam \DMAout~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_26,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
maxii_io \nNMIout~I (
	.datain(vcc),
	.oe(vcc),
	.combout(),
	.padio(nNMIout));
// synopsys translate_off
defparam \nNMIout~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
maxii_io \nIRQout~I (
	.datain(vcc),
	.oe(vcc),
	.combout(),
	.padio(nIRQout));
// synopsys translate_off
defparam \nIRQout~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
maxii_io \nRDYout~I (
	.datain(vcc),
	.oe(vcc),
	.combout(),
	.padio(nRDYout));
// synopsys translate_off
defparam \nRDYout~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_27,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
maxii_io \nINHout~I (
	.datain(vcc),
	.oe(vcc),
	.combout(),
	.padio(nINHout));
// synopsys translate_off
defparam \nINHout~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_33,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
maxii_io \RWout~I (
	.datain(vcc),
	.oe(vcc),
	.combout(),
	.padio(RWout));
// synopsys translate_off
defparam \RWout~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_21,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
maxii_io \nDMAout~I (
	.datain(vcc),
	.oe(vcc),
	.combout(),
	.padio(nDMAout));
// synopsys translate_off
defparam \nDMAout~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_19,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \RAdir~I (
	.datain(vcc),
	.oe(vcc),
	.combout(),
	.padio(RAdir));
// synopsys translate_off
defparam \RAdir~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_17,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \RDdir~I (
	.datain(!\comb~2_combout ),
	.oe(vcc),
	.combout(),
	.padio(RDdir));
// synopsys translate_off
defparam \RDdir~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_69,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \SBA[0]~I (
	.datain(\SBA[0]~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(SBA[0]));
// synopsys translate_off
defparam \SBA[0]~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_71,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \SBA[1]~I (
	.datain(\SBA[1]~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(SBA[1]));
// synopsys translate_off
defparam \SBA[1]~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_75,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \SA[0]~I (
	.datain(\SA[0]~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(SA[0]));
// synopsys translate_off
defparam \SA[0]~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_81,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \SA[1]~I (
	.datain(\SA[1]~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(SA[1]));
// synopsys translate_off
defparam \SA[1]~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_82,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \SA[2]~I (
	.datain(\SA[2]~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(SA[2]));
// synopsys translate_off
defparam \SA[2]~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_84,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \SA[3]~I (
	.datain(\SA[3]~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(SA[3]));
// synopsys translate_off
defparam \SA[3]~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_76,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \SA[4]~I (
	.datain(\SA[4]~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(SA[4]));
// synopsys translate_off
defparam \SA[4]~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_83,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \SA[5]~I (
	.datain(\SA[5]~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(SA[5]));
// synopsys translate_off
defparam \SA[5]~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_77,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \SA[6]~I (
	.datain(\SA[6]~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(SA[6]));
// synopsys translate_off
defparam \SA[6]~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_78,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \SA[7]~I (
	.datain(\SA[7]~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(SA[7]));
// synopsys translate_off
defparam \SA[7]~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_74,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \SA[8]~I (
	.datain(\SA[8]~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(SA[8]));
// synopsys translate_off
defparam \SA[8]~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_72,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \SA[9]~I (
	.datain(\SA[9]~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(SA[9]));
// synopsys translate_off
defparam \SA[9]~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_73,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \SA[10]~I (
	.datain(\SA[10]~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(SA[10]));
// synopsys translate_off
defparam \SA[10]~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_70,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \SA[11]~I (
	.datain(\SA[11]~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(SA[11]));
// synopsys translate_off
defparam \SA[11]~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_68,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \SA[12]~I (
	.datain(\SA[12]~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(SA[12]));
// synopsys translate_off
defparam \SA[12]~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_67,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \nRCS~I (
	.datain(!\nRCS~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(nRCS));
// synopsys translate_off
defparam \nRCS~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_62,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \nRAS~I (
	.datain(!\nRAS~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(nRAS));
// synopsys translate_off
defparam \nRAS~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_61,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \nCAS~I (
	.datain(!\nCAS~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(nCAS));
// synopsys translate_off
defparam \nCAS~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_58,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \nSWE~I (
	.datain(!\nSWE~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(nSWE));
// synopsys translate_off
defparam \nSWE~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_85,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \DQML~I (
	.datain(!\DQML~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(DQML));
// synopsys translate_off
defparam \DQML~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_57,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \DQMH~I (
	.datain(!\DQMH~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(DQMH));
// synopsys translate_off
defparam \DQMH~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_66,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \RCKE~I (
	.datain(!\RCKE~reg0_regout ),
	.oe(vcc),
	.combout(),
	.padio(RCKE));
// synopsys translate_off
defparam \RCKE~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \nFCS~I (
	.datain(!\FCS~regout ),
	.oe(\FCKOE~regout ),
	.combout(),
	.padio(nFCS));
// synopsys translate_off
defparam \nFCS~I .operation_mode = "output";
// synopsys translate_on

// Location: PIN_12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
maxii_io \FCK~I (
	.datain(\FCKout~regout ),
	.oe(\FCKOE~regout ),
	.combout(),
	.padio(FCK));
// synopsys translate_off
defparam \FCK~I .bus_hold = "true";
defparam \FCK~I .operation_mode = "output";
// synopsys translate_on

endmodule
