Apple-2-HW/GR8RAM
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Clean up

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This commit is contained in:
Zane Kaminski 2023-04-14 00:59:54 -04:00
parent dd6dad0b98
commit 78ff51995b
1 changed files with 63 additions and 83 deletions
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146
cpld/GR8RAM.v
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@ -10,32 +10,21 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
reg PHI0r1, PHI0r2;
always @(posedge C25M) begin PHI0r1 <= PHI0; PHI0r2 <= PHI0r1; end
/* Reset filter */
input nRES;
reg [3:0] nRESf = 0;
reg nRESr = 0;
/* Reset synchronization */
input nRES; reg nRESr = 0;
always @(posedge C25M) begin
nRESf[3:0] <= { nRESf[2:0], nRES };
nRESr <= nRESf[3] || nRESf[2] || nRESf[1] || nRESf[0];
if (PS==15) nRESr <= nRES;
end
/* Firmware select */
input [1:0] SetFW;
reg [1:0] SetFWr;
reg SetFWLoaded = 0;
always @(posedge C25M) begin
if (~SetFWLoaded) begin
SetFWLoaded <= 1;
SetFWr[1:0] <= SetFW[1:0];
end
end
wire [1:0] SetROM = ~SetFWr[1:0];
wire SetEN16MB = SetROM[1:0]==2'b11;
wire [1:0] SetROM = ~SetFW[1:0];
wire SetEN16MB = 0;//SetROM[1:0]==2'b11;
wire SetEN24bit = SetROM[1];
/* State counter from PHI0 rising edge */
reg [3:0] PS = 0;
wire PSStart = PS==0 && PHI0r1 && ~PHI0r2;
wire PSStart = PS==0 && PHI0r1 && !PHI0r2;
always @(posedge C25M) begin
if (PSStart) PS <= 1;
else if (PS==0) PS <= 0;
@ -64,53 +53,39 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
input nIOSEL, nDEVSEL, nIOSTRB;
/* Apple address bus */
input [15:0] RA; input nWE;
reg [11:0] RAr; reg nWEr;
reg CXXXr;
always @(posedge PHI0) begin
CXXXr <= RA[15:12]==4'hC;
RAr[11:0] <= RA[11:0];
nWEr <= nWE;
end
input [15:0] RA; reg CXXXr;
input nWE;
always @(posedge PHI0) CXXXr <= RA[15:12]==4'hC;
/* Apple select signals */
wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (~RAr[11]));
wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN;
wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF;
wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3;
wire RAMSpecSEL = RAMRegSpecSEL && (~SetEN24bit || SetEN16MB || ~Addr[23]);
wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2;
wire AddrMSpecSEL = REGSpecSEL && RAr[3:0]==4'h1;
wire AddrLSpecSEL = REGSpecSEL && RAr[3:0]==4'h0;
wire BankSEL = REGEN && ~nDEVSEL && BankSpecSEL;
wire RAMRegSEL = ~nDEVSEL && RAMRegSpecSEL;
wire RAMSEL = ~nDEVSEL && RAMSpecSEL;
wire RAMWR = RAMSEL && ~nWEr;
wire AddrHSEL = REGEN && ~nDEVSEL && AddrHSpecSEL;
wire AddrMSEL = REGEN && ~nDEVSEL && AddrMSpecSEL;
wire AddrLSEL = REGEN && ~nDEVSEL && AddrLSpecSEL;
wire RAMExists = (~SetEN24bit || SetEN16MB || ~Addr[23]);
wire BankSEL = REGEN && !nDEVSEL && RA[3:0]==4'hF;
wire RAMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h3;
wire AddrHSEL = REGEN && !nDEVSEL && RA[3:0]==4'h2;
wire AddrMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h1;
wire AddrLSEL = REGEN && !nDEVSEL && RA[3:0]==4'h0;
/* IOROMEN and REGEN control */
/* IOROMEN control */
reg IOROMEN = 0;
reg REGEN = 0;
reg nIOSTRBr;
wire IOROMRES = RAr[10:0]==11'h7FF && ~nIOSTRB && ~nIOSTRBr;
always @(posedge C25M, negedge nRESr) begin
if (~nRESr) REGEN <= 0;
else if (PS==8 && ~nIOSEL) REGEN <= 1;
wire IOROMRES = !nIOSTRB && RA[10:0]==11'h7FF;
always @(posedge C25M, posedge IOROMRES) begin
if (IOROMRES) IOROMEN <= 0;
else if (!nRESr) IOROMEN <= 0;
else if (!nIOSEL) IOROMEN <= 1;
end
always @(posedge C25M) begin
nIOSTRBr <= nIOSTRB;
if (~nRESr) IOROMEN <= 0;
else if (PS==8 && IOROMRES) IOROMEN <= 0;
else if (PS==8 && ~nIOSEL) IOROMEN <= 1;
/* REGEN control */
reg REGEN = 0;
always @(posedge C25M, negedge nRESr) begin
if (!nRESr) REGEN <= 0;
else if (!nIOSEL) REGEN <= 1;
end
/* Apple data bus */
inout [7:0] RD = RDdir ? 8'bZ : RDD[7:0];
reg [7:0] RDD;
output RDdir = ~(PHI0r2 && nWE && PHI0 &&
(~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOROMEN && RA[10:0]!=11'h7FF)));
output RDdir = !(PHI0r2 && nWE && PHI0 &&
((!nDEVSEL && RAMExists) || !nIOSEL || (!nIOSTRB && IOROMEN)));
/* Slinky address registers */
reg [23:0] Addr = 0;
@ -118,16 +93,16 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
reg AddrIncM = 0;
reg AddrIncH = 0;
always @(posedge C25M, negedge nRESr) begin
if (~nRESr) begin
if (!nRESr) begin
Addr[23:0] <= 24'h000000;
AddrIncL <= 0;
AddrIncM <= 0;
AddrIncH <= 0;
end else begin
if (PS==8 && RAMRegSEL) AddrIncL <= 1;
if (PS==8 && RAMSEL) AddrIncL <= 1;
else AddrIncL <= 0;
if (PS==8 && AddrLSEL && ~nWEr) begin
if (PS==8 && AddrLSEL && !nWE) begin
Addr[7:0] <= RD[7:0];
AddrIncM <= Addr[7] && ~RD[7];
end else if (AddrIncL) begin
@ -135,7 +110,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
AddrIncM <= Addr[7:0]==8'hFF;
end else AddrIncM <= 0;
if (PS==8 && AddrMSEL && ~nWEr) begin
if (PS==8 && AddrMSEL && !nWE) begin
Addr[15:8] <= RD[7:0];
AddrIncH <= Addr[15] && ~RD[7];
end else if (AddrIncM) begin
@ -143,7 +118,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
AddrIncH <= Addr[15:8]==8'hFF;
end else AddrIncH <= 0;
if (PS==8 && AddrHSEL && ~nWEr) begin
if (PS==8 && AddrHSEL && !nWE) begin
Addr[23:16] <= RD[7:0];
end else if (AddrIncH) begin
Addr[23:16] <= Addr[23:16]+1;
@ -151,12 +126,14 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
end
end
/* ROM bank register */
/* ROM bank register and restore state */
reg Bank = 0;
reg RestoreDone = 0;
always @(posedge C25M, negedge nRESr) begin
if (~nRESr) Bank <= 0;
else if (PS==8 && BankSEL && ~nWEr) begin
else if (PS==8 && BankSEL && !nWE) begin
Bank <= RD[0];
if (RD[0]) RestoreDone <= 1;
end
end
@ -327,10 +304,13 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
/* Apple data bus from SDRAM */
always @(negedge C25M) begin
if (PS==5) begin
if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0];
else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8];
else if (AddrHSpecSEL) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
else RDD[7:0] <= SD[7:0];
if (!nDEVSEL) case (RA[3:0])
4'h0: RDD[7:0] <= Addr[7:0];
4'h1: RDD[7:0] <= Addr[15:8];
4'h2: RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
4'h3: RDD[7:0] <= SD[7:0];
default: RDD[7:0] <= SD[7:0];
endcase else RDD[7:0] <= SD[7:0];
end
end
@ -344,28 +324,28 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
always @(posedge C25M) begin
case (PS[3:0])
0: begin // NOP CKE / NOP CKD
RCKE <= PSStart && (IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
RCKE <= PSStart && (IS==6 || (IS==7 && CXXXr));
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 1: begin // ACT CKE / NOP CKD (ACT)
RCKE <= IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL));
nRCS <= ~(IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
RCKE <= RCKE;
nRCS <= !RCKE;
nRAS <= 0;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 2: begin // RD CKE / NOP CKD (RD)
RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
nRCS <= ~(IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL));
RCKE <= RCKE;
nRCS <= !RCKE;
nRAS <= 1;
nCAS <= 0;
nSWE <= 1;
SDOE <= 0;
end 3: begin // NOP CKE / CKD
RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
RCKE <= RCKE;
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
@ -393,19 +373,19 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
nSWE <= 1;
SDOE <= 0;
end 7: begin // NOP CKE / CKD
RCKE <= IS==6 || (RAMWR && IS==7);
RCKE <= IS==6 || (RAMSEL && !nWE && IS==7);
nRCS <= 1;
nRAS <= 1;
nCAS <= 1;
nSWE <= 1;
SDOE <= 0;
end 8: begin // WR AP CKE / NOP CKD (WR AP)
RCKE <= IS==6 || (RAMWR && IS==7);
nRCS <= ~(IS==6 || (RAMWR && IS==7));
RCKE <= RCKE;
nRCS <= !RCKE;
nRAS <= 1;
nCAS <= 0;
nSWE <= 0;
SDOE <= IS==6 || (RAMWR && IS==7);
SDOE <= RCKE;
end 9: begin // NOP CKE / NOP CKD
RCKE <= 1;
nRCS <= 1;
@ -421,8 +401,8 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
nSWE <= 0;
SDOE <= 0;
end 11: begin // LDM CKE / AREF CKE / NOP CKD
RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
nRCS <= ~(IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd));
RCKE <= RCKE;
nRCS <= !RCKE;
nRAS <= 0;
nCAS <= 0;
nSWE <= ~(IS==1);
@ -456,25 +436,25 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
if (IS==6) begin
SBA[1:0] <= { 2'b10 };
SA[12:0] <= { 10'b0011000100, LS[12:10] };
end else if (RAMSpecSEL) begin
end else if (nIOSEL && nIOSTRB) begin
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000;
SA[9:0] <= Addr[19:10];
end else begin
SBA[1:0] <= 2'b10;
SA[12:0] <= { 10'b0011000100, Bank, RAr[11:10] };
SA[12:0] <= { 10'b0011000100, Bank, RA[11:10] };
end
end 2: begin // RD
if (RAMSpecSEL) begin
if (nIOSEL && nIOSTRB) begin
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
SA[12:0] <= { 4'b0011, Addr[9:1] };
DQML <= Addr[0];
DQMH <= ~Addr[0];
end else begin
SBA[1:0] <= 2'b10;
SA[12:0] <= { 4'b0011, RAr[9:1]};
DQML <= RAr[0];
DQMH <= ~RAr[0];
SA[12:0] <= { 4'b0011, RA[9:1]};
DQML <= RA[0];
DQMH <= ~RA[0];
end
end 3: begin // NOP CKE
DQML <= 1'b1;